[{"data":1,"prerenderedAt":64},["ShallowReactive",2],{"blog-4-layer-vs-6-layer-pcb-stackup-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":26,"slug":32,"sourceLocale":33,"availableLocales":34,"jsonld":40},"4-Layer vs 6-Layer PCB Stackup: Reference Planes First","Choose between four and six PCB layers by checking reference planes, dielectric spacing, routing demand and power paths, with a practical stackup worksheet.","2026-11-08","design","/assets/img/blogs/2026/11/4-layer-vs-6-layer-pcb-stackup-cover.svg",6,1182,"PT6M","\u003Cp>Choose four or six layers by checking whether the required routes have suitable reference planes, achievable geometries and enough routing space. Six layers can provide more routing and plane options, but the layer count alone does not establish impedance control or signal integrity.\u003C/p>\n\u003Cp>Start with the \u003Ca href=\"/en/tools/pcb-impedance-calculator/\">PCB impedance and stackup workbench\u003C/a> to compare constructions and signal-layer choices. Treat its candidates as planning inputs until the fabricator confirms cured dielectric thicknesses, materials, copper and tolerances.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/img/blogs/2026/11/4-layer-vs-6-layer-pcb-stackup.svg\" alt=\"Illustrative four-layer and six-layer assignments; adjacent signal routes reference ground while power and signal roles require explicit review\">\u003C/p>\n\u003Ch2>When is a four-layer board a reasonable starting point?\u003C/h2>\n\u003Cp>A four-layer board can work well when placement and routing allow the important signals to stay near continuous references and the power distribution fits the remaining copper. A common starting assignment is L1 signal, L2 ground, L3 power and L4 signal.\u003C/p>\n\u003Cp>That shorthand hides a key review question: L4 is adjacent to L3. If L3 is split into several rails, a bottom route can cross a reference discontinuity. Even a continuous power plane needs an appropriate AC return connection to ground when a signal transition changes reference. Calling every internal copper layer a ground plane in a calculator does not make it one physically.\u003C/p>\n\u003Cp>Another four-layer approach uses ground on both inner layers and distributes power with outer-layer copper. It can give both outer signal layers a ground reference, at the cost of routing and power-distribution space. Compare the actual copper roles and placement rather than assuming one assignment is universally best.\u003C/p>\n\u003Ch2>What can six layers add?\u003C/h2>\n\u003Cp>An illustrative six-layer assignment is L1 signal, L2 ground, L3 signal/power, L4 signal/power, L5 ground and L6 signal. Both outer layers can then be adjacent to ground, while additional internal copper can help with routing and power distribution.\u003C/p>\n\u003Cp>The middle layers still require a physical cross-section review. Their relationship to both ground planes, each other and any power regions depends on the dielectric spacings and copper patterns. Do not assume that every L3/L4 route behaves as an isolated stripline merely because the board has six layers. Nearby signal copper can create coupling.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Review question\u003C/th>\n\u003Cth>Four-layer route to acceptance\u003C/th>\n\u003Cth>Reason to investigate six layers\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Can critical routes keep a continuous reference?\u003C/td>\n\u003Ctd>Place and route them on layers adjacent to suitable planes\u003C/td>\n\u003Ctd>Existing assignments force repeated plane splits or reference changes\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Can the target width and pair gap be fabricated?\u003C/td>\n\u003Ctd>Confirm suitable trace-to-plane dielectric and realistic copper\u003C/td>\n\u003Ctd>Another construction provides more practical geometry\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Is there enough routing space?\u003C/td>\n\u003Ctd>Resolve placement and escape congestion without long detours\u003C/td>\n\u003Ctd>Extra routing layers reduce density pressure\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Can power paths meet drop and thermal budgets?\u003C/td>\n\u003Ctd>Use adequate pours/planes and connected via arrays\u003C/td>\n\u003Ctd>Additional copper allocation helps distribution\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Are the stack and copper distribution practical to build?\u003C/td>\n\u003Ctd>Confirm symmetry, material availability and finished thickness\u003C/td>\n\u003Ctd>A revised symmetric construction better suits the design\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>Worked planning example: total thickness is not reference height\u003C/h2>\n\u003Cp>Suppose two proposed boards are both 1.60 mm thick. Candidate A places the L1 reference plane 0.10 mm below the signal layer. Candidate B places it 0.20 mm below that layer. Both use an illustrative 0.20 mm signal width.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Parameter\u003C/th>\n\u003Cth>Candidate A\u003C/th>\n\u003Cth>Candidate B\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Overall thickness\u003C/td>\n\u003Ctd>1.60 mm\u003C/td>\n\u003Ctd>1.60 mm\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Trace-to-reference dielectric height h\u003C/td>\n\u003Ctd>0.10 mm\u003C/td>\n\u003Ctd>0.20 mm\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Trace width w\u003C/td>\n\u003Ctd>0.20 mm\u003C/td>\n\u003Ctd>0.20 mm\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Geometric ratio w/h\u003C/td>\n\u003Ctd>2.0\u003C/td>\n\u003Ctd>1.0\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The electrical cross-sections are different even though overall thickness is identical. For a common single-ended microstrip with the other inputs fixed, increasing reference height increases impedance. The table deliberately does not assign either candidate a 50 Ω result: copper thickness, material Dk, mask and the selected model still need to be specified and calculated.\u003C/p>\n\u003Cp>These spacings are hypothetical planning examples, not stocked laminations or a fabrication offer. Ask the supplier for its proposed cured stack, then use that construction for the calculation. See the \u003Ca href=\"/en/blog/online-impedance-calculator/\">impedance calculator guide\u003C/a> for the input and tolerance workflow.\u003C/p>\n\u003Ch2>How should you compare candidates in the workbench?\u003C/h2>\n\u003Col>\n\u003Cli>Enter the candidate layer count, board thickness and nominal copper, then apply the board settings.\u003C/li>\n\u003Cli>Add the actual single-ended or differential requirements, including target impedance and signal layer.\u003C/li>\n\u003Cli>Review the upper and lower references. A nearby copper layer is a reference only when the physical geometry and electrical connection support that assumption.\u003C/li>\n\u003Cli>Use \u003Cstrong>Trace width from target impedance\u003C/strong> to explore width, or \u003Cstrong>Impedance from current geometry\u003C/strong> to check a routed width and gap.\u003C/li>\n\u003Cli>For a differential pair, choose whether synthesis keeps edge gap or center pitch fixed. They describe different geometric constraints.\u003C/li>\n\u003Cli>Review section parameters and the physical stack, including explicit coating and intervening copper roles where applicable. Resolve unknown geometry before using the result.\u003C/li>\n\u003Cli>Compare viable candidates with the fabricator, including process tolerances and which artwork changes require your approval.\u003C/li>\n\u003C/ol>\n\u003Cp>Check input definitions before changing layer count. Include plane splits and nearby copper when deciding whether a candidate meets its requirements.\u003C/p>\n\u003Ch2>What else belongs in the comparison?\u003C/h2>\n\u003Cp>The \u003Ca href=\"/en/tools/pcb-trace-width-calculator/\">trace-width calculator\u003C/a> helps check current, resistance and drop. A six-layer stack does not automatically remove a narrow power neck-down. The \u003Ca href=\"/en/blog/pcb-via-current-capacity/\">via-current guide\u003C/a> explains the separate layer-transition check.\u003C/p>\n\u003Cp>More layer changes can also introduce via discontinuities. The \u003Ca href=\"/en/tools/pcb-via-inductance-calculator/\">via inductance\u003C/a> and \u003Ca href=\"/en/tools/pcb-via-parasitic-capacitance-calculator/\">via capacitance\u003C/a> tools provide geometry comparisons; neither replaces a full transition model. A good stackup can reduce unnecessary transitions through better layer assignment.\u003C/p>\n\u003Ch2>What should you send for stackup review?\u003C/h2>\n\u003Cp>Include the layer-role drawing, overall thickness and tolerance, required impedance structures, material preferences, minimum copper, critical current paths and via construction. Mark reference-plane continuity and any intentional voids. Define whether the supplier may change trace width, gap or dielectric construction and how substitutions are approved.\u003C/p>\n\u003Cp>For controlled impedance, agree the representative coupon, test method and acceptance band. \u003Ca href=\"https://www.ipc.org/test-methods\">IPC-TM-650's published test methods\u003C/a> include characteristic-impedance measurement guidance. General return-path considerations are discussed in \u003Ca href=\"https://www.ti.com/lit/an/slla414/slla414.pdf\">TI's High-Speed Layout Guidelines\u003C/a>. Use the project-required standard editions and supplier-confirmed production stack.\u003C/p>\n\u003Ch2>FAQ\u003C/h2>\n\u003C!-- faq:start -->\n\n\u003Ch3>Are six layers always better than four?\u003C/h3>\n\u003Cp>No. Six layers offer more allocation options, but placement, reference continuity, dielectric spacing and implementation determine whether those options help.\u003C/p>\n\u003Ch3>Can a four-layer PCB have controlled impedance?\u003C/h3>\n\u003Cp>Yes, when the selected construction and geometry support the targets and the fabrication/test requirements are agreed. Layer count alone is not the deciding criterion.\u003C/p>\n\u003Ch3>Does a 1.6 mm board need 1.6 mm entered as microstrip height?\u003C/h3>\n\u003Cp>No. Microstrip height is the relevant trace-to-reference spacing, as defined by the model. Total board thickness is a different dimension.\u003C/p>\n\u003Ch3>Should I choose layer count from clock frequency alone?\u003C/h3>\n\u003Cp>No. Also consider edge rate, return paths, routing density, power distribution and the complete interface requirements. A relatively slow clock can still have fast edges.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Cp>\u003Ca href=\"/en/tools/pcb-impedance-calculator/\">Compare a four-layer and six-layer candidate\u003C/a>, then \u003Ca href=\"/en/quote/\">request a PCB quote\u003C/a> with the intended references and impedance requirements attached.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/tools/pcb-impedance-calculator/\">PCB impedance and stackup workbench\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/online-impedance-calculator/\">Online PCB Impedance Calculator: Practical Guide\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/tools/pcb-trace-width-calculator/\">trace-width calculator\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-via-current-capacity/\">PCB Via Current Capacity: Barrel Resistance and Parallel Vias\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/tools/pcb-via-inductance-calculator/\">via inductance\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/tools/pcb-via-parasitic-capacitance-calculator/\">via capacitance\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote/\">request a PCB quote\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23],{"question":15,"answer":16,"answerText":16},"Are six layers always better than four?","No. Six layers offer more allocation options, but placement, reference continuity, dielectric spacing and implementation determine whether those options help.",{"question":18,"answer":19,"answerText":19},"Can a four-layer PCB have controlled impedance?","Yes, when the selected construction and geometry support the targets and the fabrication/test requirements are agreed. Layer count alone is not the deciding criterion.",{"question":21,"answer":22,"answerText":22},"Does a 1.6 mm board need 1.6 mm entered as microstrip height?","No. Microstrip height is the relevant trace-to-reference spacing, as defined by the model. Total board thickness is a different dimension.",{"question":24,"answer":25,"answerText":25},"Should I choose layer count from clock frequency alone?","No. Also consider edge rate, return paths, routing density, power distribution and the complete interface requirements. A relatively slow clock can still have fast edges.",[27,28,29,30,31],"4 layer PCB stackup","6 layer PCB stackup","reference plane","controlled impedance","PCB layer count","4-layer-vs-6-layer-pcb-stackup","en",[33,35,36,37,38,39],"de","it","cn","fr","ru",{"blog":41,"breadcrumb":50},{"@context":42,"@type":43,"headline":4,"description":5,"image":8,"url":44,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":45,"articleSection":7,"author":46,"publisher":49},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/4-layer-vs-6-layer-pcb-stackup/","4 layer PCB stackup, 6 layer PCB stackup, reference plane, controlled impedance, PCB layer count",{"@type":47,"name":48},"Organization","HILPCB",{"@type":47,"name":48},{"@context":42,"@type":51,"itemListElement":52},"BreadcrumbList",[53,58,62],{"@type":54,"position":55,"name":56,"item":57},"ListItem",1,"Home","https://hilpcb.com/",{"@type":54,"position":59,"name":60,"item":61},2,"Blog","https://hilpcb.com/en/blog/",{"@type":54,"position":63,"name":32,"item":44},3,1794155573146]