[{"data":1,"prerenderedAt":67},["ShallowReactive",2],{"blog-ipc-7351-land-pattern-standard-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":26,"slug":35,"sourceLocale":36,"availableLocales":37,"jsonld":43},"IPC-7351 Land Pattern Standard: Density Levels, Solder Fillet Math, and DFM Footprint Rules","Choose SMT land patterns using the applicable IPC method, component drawings and assembly constraints. Compare density levels, BGA pad styles and footprint release evidence.","2026-10-15","technology",null,10,1895,"PT10M","\u003Cp>A surface-mount footprint must fit the exact component termination and the intended fabrication, solder-paste and placement process. Use the component maker’s package-specific recommendation together with the applicable IPC methodology; neither a generic library entry nor a standard number alone verifies the finished joint.\u003C/p>\n\u003Cp>IPC-7351 addresses surface-mount design and land patterns. Its \u003Ca href=\"https://www.ipc.org/TOC/IPC-7351.pdf\">publisher’s public scope\u003C/a> includes component, land, fabrication and assembly tolerances. State the contractual document and revision, and use its licensed details for a normative calculation. Verify the document’s status and package-family applicability before using its calculation details. The \u003Ca href=\"https://www.electronics.org/ipc-document-revision-table\">publisher’s revision table\u003C/a> lists IPC-7351B as no longer maintained and IPC-7352 as a separate land-pattern guideline first issued in July 2023; agree which document applies to the project.\u003C/p>\n\u003Ch2>How does the IPC 7351 mathematical model calculate solder fillet boundaries?\u003C/h2>\n\u003Cp>Land-pattern calculation combines component dimensional limits, the required fillet goals, fabrication allowances and assembly tolerances for the package family. Use the definitions and tolerance conventions of the selected method; a ± tolerance and its full range are not interchangeable inputs.\u003C/p>\n\u003Cp>A root-sum-square tolerance model needs assumptions about variation and process capability. It does not guarantee simultaneous worst-case fit, solder wetting, fatigue life or assembly yield. Review the package drawing and the supplier’s actual process alongside any automated calculation.\u003C/p>\n\u003Cp>As a simple \u003Cstrong>geometric example\u003C/strong>, assume two equal rectangular lands with a 2.40 mm outer span and a 0.80 mm inner gap. Each land is \u003Ccode>(2.40 − 0.80) / 2 = 0.80 mm\u003C/code> long, and their center-to-center spacing is \u003Ccode>(2.40 + 0.80) / 2 = 1.60 mm\u003C/code>. These assumed dimensions illustrate a drawing check, not an IPC-recommended footprint. Add component, fabrication, placement, mask and paste requirements before adopting dimensions.\u003C/p>\n\u003Ch2>IPC-7351B Density Level A, B, or C: which protrusion tier fits your board?\u003C/h2>\n\u003Cp>Density levels describe different land protrusion choices for supported package families. They are separate from IPC product acceptance classes and do not select an end-use industry or guarantee joint strength.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Decision\u003C/th>\n\u003Cth>Level A: more protrusion\u003C/th>\n\u003Cth>Level B: nominal protrusion\u003C/th>\n\u003Cth>Level C: less protrusion\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Toe, heel and side goals\u003C/td>\n\u003Ctd>Use the package-family values in the selected method\u003C/td>\n\u003Ctd>Use the corresponding nominal values\u003C/td>\n\u003Ctd>Use the corresponding reduced values\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Space and inspection\u003C/td>\n\u003Ctd>Check extra land area against neighbors and access\u003C/td>\n\u003Ctd>Balance geometry with assembly access\u003C/td>\n\u003Ctd>Check reduced margin and inspection access\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Placement and printing\u003C/td>\n\u003Ctd>Confirm the actual equipment and paste process\u003C/td>\n\u003Ctd>Confirm the actual equipment and paste process\u003C/td>\n\u003Ctd>Verify the smaller process window on representative builds\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Mechanical loading\u003C/td>\n\u003Ctd>Validate the joint and board under the mission load\u003C/td>\n\u003Ctd>Validate the same mission requirements\u003C/td>\n\u003Ctd>Do not infer failure or suitability solely from the level\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Rework\u003C/td>\n\u003Ctd>Check iron/nozzle access and permitted heat exposure\u003C/td>\n\u003Ctd>Agree the rework process\u003C/td>\n\u003Ctd>Check whether density restricts rework access\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Release evidence\u003C/td>\n\u003Ctd>Reviewed footprint, paste/mask and first article\u003C/td>\n\u003Ctd>Same evidence for the selected construction\u003C/td>\n\u003Ctd>Same evidence plus any process checks the risk plan requires\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Choose the level with the component and assembler, then document the reason and exceptions. Select reflow and \u003Ca href=\"/en/blog/solder-paste-inspection-spi/\">3D SPI\u003C/a> coverage from the process risks and acceptance plan.\u003C/p>\n\u003Ch2>Micro-BGA pad design: NSMD versus SMD reliability\u003C/h2>\n\u003Cp>BGA land and solder-mask geometry must follow the selected package’s recommendations and the qualified assembly process.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Decision\u003C/th>\n\u003Cth>NSMD\u003C/th>\n\u003Cth>SMD\u003C/th>\n\u003Cth>What to verify\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Pad definition\u003C/td>\n\u003Ctd>Copper defines the wettable land; mask opening is larger\u003C/td>\n\u003Ctd>Mask opening defines the exposed area over a larger copper land\u003C/td>\n\u003Ctd>Exact package recommendation and artwork\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Registration\u003C/td>\n\u003Ctd>Mask must remain clear of the intended land\u003C/td>\n\u003Ctd>Mask overlap must remain controlled\u003C/td>\n\u003Ctd>Copper/mask tolerances and available web\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Solder interaction\u003C/td>\n\u003Ctd>Solder may wet the copper sidewall\u003C/td>\n\u003Ctd>Mask constrains the exposed wettable area\u003C/td>\n\u003Ctd>Ball, land, paste and reflow compatibility\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Mechanical behavior\u003C/td>\n\u003Ctd>Construction and loading determine reliability\u003C/td>\n\u003Ctd>Construction and loading determine reliability\u003C/td>\n\u003Ctd>Board support and qualification results\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Escape routing\u003C/td>\n\u003Ctd>Review copper, mask and route geometry together\u003C/td>\n\u003Ctd>Review the same constraints\u003C/td>\n\u003Ctd>Manufacturability of the actual pitch and stackup\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>AMD recommends NSMD for the BGA packages covered by its \u003Ca href=\"https://docs.amd.com/r/en-US/am013-versal-pkg-pinout/Recommended-PCB-Design-Rules-for-BGA\">AM013 design rules\u003C/a>. Other package guidance can differ; TI’s \u003Ca href=\"https://www.ti.com/quality-reliability/faqs.html\">package-specific assembly FAQ\u003C/a> discusses both definitions. Neither a universal pitch cutoff nor an automatic NSMD-to-SMD substitution is justified.\u003C/p>\n\u003Ch2>Thermal symmetry and tombstoning prevention on passive components\u003C/h2>\n\u003Cp>Tombstoning (the Manhattan effect) occurs when a two-terminal passive chip component (such as an 0402 or 0603 resistor or capacitor) lifts vertically onto one metallized end during reflow soldering, resulting in an open circuit:\u003C/p>\n\u003Cp>Unequal wetting forces can lift a two-terminal component during reflow. Pad geometry, copper heat paths, paste deposit, termination finish, placement and the thermal profile can contribute; a fixed one- or two-second timing difference is not a universal failure threshold.\u003C/p>\n\u003Ch3>Footprint and process checks for tombstoning\u003C/h3>\n\u003Col>\n\u003Cli>Compare copper connections and thermal behavior at both ends. Thermal relief is one option where compatible with current and thermal requirements, not a rule to isolate every power pad.\u003C/li>\n\u003Cli>Review land and paste symmetry with the component recommendation; identical visible trace widths do not by themselves guarantee thermal balance.\u003C/li>\n\u003Cli>Verify placement and paste release on the actual assembly.\u003C/li>\n\u003Cli>Agree mask-web limits with the fabricator and assembler for that pitch, finish and stencil.\u003C/li>\n\u003C/ol>\n\u003Ch2>Troubleshooting SMT solder defects caused by CAD footprint errors\u003C/h2>\n\u003Cp>Use the observed defect to investigate competing causes; it is not proof of one footprint error.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Defect\u003C/th>\n\u003Cth>Evidence to inspect\u003C/th>\n\u003Cth>Candidate footprint/process action\u003C/th>\n\u003Cth>Release check\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Tombstoning\u003C/td>\n\u003Ctd>Pad/copper/paste symmetry and thermal profile\u003C/td>\n\u003Ctd>Review land geometry, copper heat paths and paste\u003C/td>\n\u003Ctd>Representative reflow and inspection\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Bridging\u003C/td>\n\u003Ctd>Exact lead/pad pitch, mask web, paste and placement\u003C/td>\n\u003Ctd>Review the package land pattern and stencil together\u003C/td>\n\u003Ctd>Agreed workmanship and electrical checks\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>BGA voiding or cracking\u003C/td>\n\u003Ctd>Imaging, thermal history and failure analysis as needed\u003C/td>\n\u003Ctd>Review pad definition, via treatment, paste, profile and support\u003C/td>\n\u003Ctd>Package/customer-specific acceptance and qualification\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Insufficient fillet or open\u003C/td>\n\u003Ctd>Lead dimensions, placement, solderability and heat exposure\u003C/td>\n\u003Ctd>Correct verified dimensional or process mismatches\u003C/td>\n\u003Ctd>Applicable termination/class criteria\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Rotation or floating\u003C/td>\n\u003Ctd>Land/paste distribution, placement and profile\u003C/td>\n\u003Ctd>Review geometry and deposit balance\u003C/td>\n\u003Ctd>First-article orientation and joint inspection\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>SMT economics: how footprint standardization prevents scrap and delays\u003C/h2>\n\u003Cp>Controlled libraries can reduce avoidable changes, but benefits require project data rather than universal yield or savings claims.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Decision\u003C/th>\n\u003Cth>Risk in an uncontrolled library\u003C/th>\n\u003Cth>Evidence for a controlled library\u003C/th>\n\u003Cth>Commercial consequence to compare\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Initial assembly\u003C/td>\n\u003Ctd>Unreviewed package or paste mismatch\u003C/td>\n\u003Ctd>Package-to-footprint review and first article\u003C/td>\n\u003Ctd>Rework and investigation on the actual build\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Stencil release\u003C/td>\n\u003Ctd>Paste apertures not reviewed with the package mix\u003C/td>\n\u003Ctd>Approved aperture/thickness plan\u003C/td>\n\u003Ctd>Tooling and revision cost quoted by the assembler\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Placement\u003C/td>\n\u003Ctd>Origin/rotation assumptions differ\u003C/td>\n\u003Ctd>Verified import and first-article orientation\u003C/td>\n\u003Ctd>Setup time and repeatability\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Maintenance\u003C/td>\n\u003Ctd>Duplicate footprints lack ownership\u003C/td>\n\u003Ctd>Controlled revision and approved source data\u003C/td>\n\u003Ctd>Engineering effort and change risk\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Alternate sourcing\u003C/td>\n\u003Ctd>Similar names hide pin/package differences\u003C/td>\n\u003Ctd>Electrical, mechanical and process approval of each alternate\u003C/td>\n\u003Ctd>Availability versus requalification cost\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>A common footprint does not make alternate MPNs electrically, thermally or mechanically interchangeable. Review our \u003Ca href=\"/en/products/pcb-assembly/\">PCB assembly\u003C/a> and \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a> scope when assigning the design-to-manufacturing checks.\u003C/p>\n\u003Ch2>Submit / Release Aid\u003C/h2>\n\u003Cp>\u003Cstrong>Send with the RFQ or release package:\u003C/strong>\u003C/p>\n\u003Col>\n\u003Cli>Gerber (\u003Ccode>RS-274X\u003C/code> / \u003Ccode>Gerber X2\u003C/code>) or \u003Ccode>ODB++\u003C/code> / \u003Ccode>IPC-2581\u003C/code> archive containing copper (\u003Ccode>GTL\u003C/code>/\u003Ccode>GBL\u003C/code>), solder mask (\u003Ccode>GTS\u003C/code>/\u003Ccode>GBS\u003C/code>), and paste mask (\u003Ccode>GTP\u003C/code>/\u003Ccode>GBP\u003C/code>) layers.\u003C/li>\n\u003Cli>Pick-and-Place centroid file (\u003Ccode>XYR\u003C/code>) with a stated component origin, side and rotation convention verified against the assembly drawing.\u003C/li>\n\u003Cli>Complete Bill of Materials (\u003Ca href=\"/en/blog/what-is-a-bom/\">BOM\u003C/a>) with full Manufacturer Part Numbers (MPNs) so package body tolerances can be verified against CAD footprints.\u003C/li>\n\u003Cli>Assembly drawing noting selected land-pattern method, density level where applicable and approved exceptions and any Via-in-Pad Plated Over (\u003Ccode>VIPPO\u003C/code>, IPC-4761 Type VII) locations.\u003C/li>\n\u003C/ol>\n\u003Cp>\u003Cstrong>Request from the supplier (evidence you need before sign-off):\u003C/strong>\u003C/p>\n\u003Col>\n\u003Cli>Pre-build DFM / DFA footprint audit report flagging any pad-to-lead mismatches, unreviewed thermal connections or mask features outside the agreed process limits.\u003C/li>\n\u003Cli>Stencil check plot confirming aperture geometry, area ratio and paste-release requirements for the selected stencil/process and windowpane thermal-pad segmentation on QFN/DFN packages.\u003C/li>\n\u003Cli>Agreed first-article inspection records for accessible fillets and selected hidden-joint risks; identify imaging limitations and any further tests.\u003C/li>\n\u003Cli>Verification of Pin-1 polarity alignment across all polarized diodes, capacitors, and ICs prior to reflow.\u003C/li>\n\u003C/ol>\n\u003Cp>\u003Cstrong>Owner for each step:\u003C/strong>\u003C/p>\n\u003Cul>\n\u003Cli>Designer: Approve package-specific land/paste/mask geometry, thermal connections and the documented library/import convention.\u003C/li>\n\u003Cli>Quality: Approve stencil aperture reductions, verify solder mask dam integrity, and sign off on FAI fillet and X-ray voiding criteria.\u003C/li>\n\u003Cli>Procurement: Ensure alternate AVL MPNs share approved electrical, pinout, mechanical, thermal and assembly compatibility before approving substitutions.\u003C/li>\n\u003C/ul>\n\u003Cp>\u003Cstrong>Gate for verification (release decision by stage):\u003C/strong>\u003C/p>\n\u003Cul>\n\u003Cli>EVT: Automated CAD footprint-to-MPN package overlay check + FAI on the first prototype boards.\u003C/li>\n\u003Cli>DVT: Inline \u003Ca href=\"/en/blog/solder-paste-inspection-spi/\">3D solder paste inspection (SPI)\u003C/a> Cpk volume check + post-reflow 3D AOI fillet inspection.\u003C/li>\n\u003Cli>PVT: Validate feeder setup, placement, profile, inspection coverage and agreed pilot acceptance.\u003C/li>\n\u003Cli>MP: Continuous statistical process control (SPC) across stencil printing, placement, and AOI inspection gates.\u003C/li>\n\u003C/ul>\n\u003Cp>When your CAD library and component footprints are ready for manufacturing verification, explore our \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a>, \u003Ca href=\"/en/products/turnkey-assembly/\">turnkey PCB assembly\u003C/a>, and \u003Ca href=\"/en/services/pcb-design/\">PCB design services\u003C/a>, or upload your files to \u003Ca href=\"/en/quote/\">request a quote\u003C/a>.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch3>How should IPC-7351 Density Levels A, B and C be selected?\u003C/h3>\n\u003Cp>Levels A, B and C use different protrusion goals for supported package families. Select the level using the applicable method, component recommendation and assembly process. The level alone does not determine yield, an industry qualification or mandatory inspection equipment.\u003C/p>\n\u003Ch3>Why is NSMD preferred over SMD for fine-pitch BGA pads?\u003C/h3>\n\u003Cp>NSMD exposes the copper perimeter and is recommended by many package guides. The correct choice remains package- and process-specific; verify the maker’s land/mask dimensions and the actual fabrication tolerances rather than applying one rule to every fine-pitch BGA.\u003C/p>\n\u003Ch3>How does an unbalanced footprint cause chip component tombstoning?\u003C/h3>\n\u003Cp>Unequal wetting and thermal behavior can create a lifting torque. Compare both pads’ geometry, copper heat paths, paste, termination and placement, then validate the profile and corrective change on the actual assembly.\u003C/p>\n\u003Ch3>Does IPC-7351 define component pin-1 orientation conventions?\u003C/h3>\n\u003Cp>Land-pattern conventions can support consistent libraries, but the manufacturing handoff must state and verify the origin, side, pin-one and rotation mapping. Do not assume every rectangular part uses a universal northwest pin-one rule or that a centroid file needs no import check.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Cscript type=\"application/ld+json\">\n{\n  \"@context\": \"https://schema.org\",\n  \"@type\": \"TechArticle\",\n  \"headline\": \"IPC-7351 Land Pattern Standard: Density Levels, Solder Fillet Math, and DFM Footprint Rules\",\n  \"description\": \"Choose SMT land patterns using the applicable IPC method, component drawings and assembly constraints. Compare density levels, BGA pad styles and footprint release evidence.\",\n  \"datePublished\": \"2026-10-15\",\n  \"author\": {\n    \"@type\": \"Organization\",\n    \"name\": \"HilPCB\"\n  },\n  \"publisher\": {\n    \"@type\": \"Organization\",\n    \"name\": \"HilPCB\"\n  },\n  \"about\": {\n    \"@type\": \"Thing\",\n    \"name\": \"IPC-7351 Land Pattern Standard\"\n  },\n  \"keywords\": [\"ipc-7351\", \"ipc 7351\", \"smt land pattern\", \"footprint standard\", \"density levels\", \"nsmd vs smd\", \"tombstoning prevention\", \"solder fillet math\"]\n}\n\u003C/script>\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/solder-paste-inspection-spi/\">What Is Solder Paste Inspection (SPI)? Measurements and Print Release\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/pcb-assembly/\">PCB assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/what-is-a-bom/\">What Is a BOM in Electronics Manufacturing? PCBA BOM Format, Sample Table, and Sourcing Rules\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/turnkey-assembly/\">turnkey PCB assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/services/pcb-design/\">PCB design services\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote/\">request a quote\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23],{"question":15,"answer":16,"answerText":16},"How should IPC-7351 Density Levels A, B and C be selected?","Levels A, B and C use different protrusion goals for supported package families. Select the level using the applicable method, component recommendation and assembly process. The level alone does not determine yield, an industry qualification or mandatory inspection equipment.",{"question":18,"answer":19,"answerText":19},"Why is NSMD preferred over SMD for fine-pitch BGA pads?","NSMD exposes the copper perimeter and is recommended by many package guides. The correct choice remains package- and process-specific; verify the maker’s land/mask dimensions and the actual fabrication tolerances rather than applying one rule to every fine-pitch BGA.",{"question":21,"answer":22,"answerText":22},"How does an unbalanced footprint cause chip component tombstoning?","Unequal wetting and thermal behavior can create a lifting torque. Compare both pads’ geometry, copper heat paths, paste, termination and placement, then validate the profile and corrective change on the actual assembly.",{"question":24,"answer":25,"answerText":25},"Does IPC-7351 define component pin-1 orientation conventions?","Land-pattern conventions can support consistent libraries, but the manufacturing handoff must state and verify the origin, side, pin-one and rotation mapping. Do not assume every rectangular part uses a universal northwest pin-one rule or that a centroid file needs no import check.",[27,28,29,30,31,32,33,34],"ipc-7351","ipc 7351","smt land pattern","pcb footprint standard","density level a b c","nsmd vs smd bga","smt pad design","dfm footprints","ipc-7351-land-pattern-standard","en",[36,38,39,40,41,42],"de","it","cn","fr","ru",{"blog":44,"breadcrumb":53},{"@context":45,"@type":46,"headline":4,"description":5,"url":47,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":48,"articleSection":7,"author":49,"publisher":52},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/ipc-7351-land-pattern-standard/","ipc-7351, ipc 7351, smt land pattern, pcb footprint standard, density level a b c, nsmd vs smd bga, smt pad design, dfm footprints",{"@type":50,"name":51},"Organization","HILPCB",{"@type":50,"name":51},{"@context":45,"@type":54,"itemListElement":55},"BreadcrumbList",[56,61,65],{"@type":57,"position":58,"name":59,"item":60},"ListItem",1,"Home","https://hilpcb.com/",{"@type":57,"position":62,"name":63,"item":64},2,"Blog","https://hilpcb.com/en/blog/",{"@type":57,"position":66,"name":35,"item":47},3,1792969676110]