[{"data":1,"prerenderedAt":65},["ShallowReactive",2],{"blog-microstrip-vs-stripline-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":29,"slug":34,"sourceLocale":35,"availableLocales":36,"jsonld":41},"Microstrip vs Stripline: Choosing a PCB Routing Structure","Compare microstrip and stripline PCB transmission lines across impedance geometry, effective permittivity, propagation delay, far-end crosstalk (FEXT), via stubs, and layer stackup cost.","2026-10-30","technology","/assets/blogs/microstrip-vs-stripline/geometry.svg",12,2219,"PT12M","\u003Cp>Choosing between \u003Cstrong>microstrip\u003C/strong> and \u003Cstrong>stripline\u003C/strong> routing is not a matter of picking a fixed frequency threshold where one topology automatically replaces the other; it is a stackup and channel-architecture tradeoff between \u003Cstrong>outer-layer component access with zero via transitions\u003C/strong> (microstrip) and \u003Cstrong>homogeneous dielectric shielding with dual reference planes\u003C/strong> (stripline).\u003C/p>\n\u003Cp>Because a surface microstrip trace radiates part of its electromagnetic field into the air and solder mask above the board while a buried stripline trace is completely enclosed by dielectric and two reference planes, the two topologies behave very differently in \u003Cstrong>trace width for a given target impedance (\u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub>\u003C/span>), propagation delay (\u003Cspan class=\"math-inline\">t\u003Csub>pd\u003C/sub>\u003C/span>), far-end crosstalk (FEXT), EMI containment, and via-stub reflections\u003C/strong>.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/blogs/microstrip-vs-stripline/geometry.svg\" alt=\"Cross-sectional comparison of surface microstrip and symmetric stripline showing electric field lines, trace widths, and calculated impedance\">\u003C/p>\n\u003Ch2>1. Electromagnetic Physics: How Field Containment Changes Signal Behavior\u003C/h2>\n\u003Cp>Before running a stackup field solver, compare how the physical cross-section of each transmission line shapes its electromagnetic propagation (see \u003Ca href=\"https://www.ti.com/lit/sprabi2\">Texas Instruments KeyStone Hardware Design Guide SPRABI2D, Appendix B\u003C/a> and \u003Ca href=\"https://www.renesas.com/us/en/document/apn/1014-microstrip-vs-stripline-crosstalk-and-rms-phase-jitter\">Renesas/IDT Application Note AN-1014\u003C/a>):\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Engineering Dimension\u003C/th>\n\u003Cth>Surface Microstrip (Outer Layer)\u003C/th>\n\u003Cth>Symmetric / Offset Stripline (Inner Layer)\u003C/th>\n\u003Cth>Practical Design Impact\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Dielectric Environment\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Inhomogeneous:\u003C/strong> Substrate (\u003Cspan class=\"math-inline\">ε\u003Csub>r\u003C/sub>\u003C/span>) below, air (\u003Cspan class=\"math-inline\">ε\u003Csub>r\u003C/sub> = 1.0\u003C/span>) and LPI solder mask (\u003Cspan class=\"math-inline\">ε\u003Csub>r\u003C/sub> ≈ 3.3--3.8\u003C/span>) above\u003C/td>\n\u003Ctd>\u003Cstrong>Homogeneous (or Core + Prepreg):\u003C/strong> Completely surrounded by dielectric between two reference planes\u003C/td>\n\u003Ctd>Microstrip has a lower effective permittivity (\u003Cspan class=\"math-inline\">ε\u003Csub>eff\u003C/sub> < ε\u003Csub>r\u003C/sub>\u003C/span>); stripline sees \u003Cspan class=\"math-inline\">ε\u003Csub>eff\u003C/sub> ≈ ε\u003Csub>r\u003C/sub>\u003C/span>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Propagation Delay (\u003Cspan class=\"math-inline\">t\u003Csub>pd\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Faster\u003C/strong> (\u003Cspan class=\"math-inline\">≈ 5.4--6.0 ps/mm\u003C/span> on typical FR-4 / hydrocarbon laminates)\u003C/td>\n\u003Ctd>\u003Cstrong>Slower\u003C/strong> (\u003Cspan class=\"math-inline\">≈ 6.3--7.2 ps/mm\u003C/span> on the same dielectric material)\u003C/td>\n\u003Ctd>Never match length-for-length in mm when a bus splits across microstrip and stripline layers; \u003Cstrong>match flight time in picoseconds\u003C/strong>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Far-End Crosstalk (FEXT)\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>High FEXT:\u003C/strong> Odd-mode fields travel more in air than even-mode fields (\u003Cspan class=\"math-inline\">v\u003Csub>odd\u003C/sub> ≠ v\u003Csub>even\u003C/sub>\u003C/span>), accumulating forward crosstalk\u003C/td>\n\u003Ctd>\u003Cstrong>Near-Zero Ideal FEXT:\u003C/strong> Capacitive and inductive coupling match in a uniform medium (\u003Cspan class=\"math-inline\">v\u003Csub>odd\u003C/sub> ≈ v\u003Csub>even\u003C/sub>\u003C/span>)\u003C/td>\n\u003Ctd>Stripline allows tighter trace-to-trace pair spacing for the same crosstalk budget (\u003Ca href=\"https://www.renesas.com/us/en/document/apn/1014-microstrip-vs-stripline-crosstalk-and-rms-phase-jitter\">Renesas AN-1014\u003C/a>)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Trace Width for \u003Cspan class=\"math-inline\">50 Ω\u003C/span> (at equal nearest-plane spacing \u003Cspan class=\"math-inline\">h\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Wider trace\u003C/strong> required (single reference plane provides lower capacitance per unit width)\u003C/td>\n\u003Ctd>\u003Cstrong>Narrower trace\u003C/strong> required (dual reference planes double capacitive coupling, requiring a narrower conductor)\u003C/td>\n\u003Ctd>Stripline increases routing density per layer, but narrower copper increases DC and skin-effect conductor resistance\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Solder Mask Sensitivity\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>High:\u003C/strong> Coating over trace lowers \u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub>\u003C/span> by \u003Cspan class=\"math-inline\">≈ 2--3 Ω\u003C/span> and adds high-\u003Cspan class=\"math-inline\">\\tanδ\u003C/span> mask dielectric loss\u003C/td>\n\u003Ctd>\u003Cstrong>Zero:\u003C/strong> Buried inside internal layers, immune to surface solder mask thickness variation and external handling\u003C/td>\n\u003Ctd>Uncoated (solder-mask-relieved) microstrip is often used on \u003Cspan class=\"math-inline\">>10 GHz\u003C/span> RF launches to avoid solder-mask loss\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Via Transitions & Stubs\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>None for surface-to-surface links:\u003C/strong> Direct connection between top-side SMD pins without vias\u003C/td>\n\u003Ctd>\u003Cstrong>Requires \u003Cspan class=\"math-inline\">≥ 2\u003C/span> vias:\u003C/strong> Signal must drop from L1 pad through vias to inner layer and back up to receiver\u003C/td>\n\u003Ctd>Through-hole vias on stripline create \u003Cstrong>resonant open stubs\u003C/strong> unless routed near the bottom layer or backdrilled\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>2. Reproducible Geometry Comparison: Same Width vs. Same \u003Cspan class=\"math-inline\">50 Ω\u003C/span> Target\u003C/h2>\n\u003Cp>A frequent layout error occurs when an engineer moves a routed \u003Cspan class=\"math-inline\">50 Ω\u003C/span> trace from Layer 1 (microstrip) to Layer 3 (stripline) during congestion cleanup while leaving the CAD trace width unchanged. To illustrate the exact geometric shift without relying on a black-box proprietary solver, we can compare both cross-sections using standard analytical transmission-line equations:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Microstrip Model:\u003C/strong> Quasi-static Hammerstad–Jensen equations (\u003Ca href=\"https://qucs.sourceforge.net/tech/node75.html\">Qucs Technical Documentation, Eqs. 11.4, 11.6, 11.15–18\u003C/a>).\u003C/li>\n\u003Cli>\u003Cstrong>Centered Symmetric Stripline Model:\u003C/strong> Exact Cohn complete elliptic integral formulation (\u003Cspan class=\"math-inline\">K(k)/K(k')\u003C/span>), as implemented in \u003Ca href=\"https://docs.kicad.org/doxygen/coupled__stripline_8cpp_source.html\">KiCad's \u003Ccode>coupled_stripline.cpp\u003C/code> source\u003C/a> and documented in the \u003Ca href=\"https://www.polarinstruments.com/man/operator/Si6000b%20User%20Guide%20(A5%20format).pdf\">Polar Instruments Si6000b Technical Appendix\u003C/a>.\u003C/li>\n\u003Cli>\u003Cstrong>Controlled Comparison Inputs:\u003C/strong> Both structures share the exact same distance to the nearest reference plane (\u003Cspan class=\"math-inline\">h = 0.20 mm\u003C/span> for microstrip; total plane-to-plane spacing \u003Cspan class=\"math-inline\">B = 2h = 0.40 mm\u003C/span> for centered stripline) and a uniform dielectric constant of \u003Cspan class=\"math-inline\">ε\u003Csub>r\u003C/sub> = 3.66\u003C/span> (representative of a hydrocarbon RF laminate's design Dk; see our \u003Ca href=\"/en/blog/material-data-sheet-reading-pcb-stackup-materials/\">PCB material datasheet reading guide\u003C/a>), under ideal zero-thickness (\u003Cspan class=\"math-inline\">t = 0\u003C/span>), uncoated, lossless assumptions.\u003C/li>\n\u003C/ul>\n\u003Cp>\u003Cem>(Download and run \u003Ccode>python calculate.py\u003C/code> using standard Python 3: \u003Ca href=\"/assets/blogs/microstrip-vs-stripline/calculate.py\">calculate.py\u003C/a>, \u003Ca href=\"/assets/blogs/microstrip-vs-stripline/calculated-results.csv\">calculated-results.csv\u003C/a>, and \u003Ca href=\"/assets/blogs/microstrip-vs-stripline/README.md\">formula notes\u003C/a>.)\u003C/em>\u003C/p>\n\u003Ch3>Experiment 1: Hold Trace Width Constant at \u003Cspan class=\"math-inline\">W = 0.300 mm\u003C/span>\u003C/h3>\n\u003Cp>When the exact same \u003Cspan class=\"math-inline\">0.300 mm\u003C/span> trace width is placed \u003Cspan class=\"math-inline\">0.20 mm\u003C/span> above one plane (microstrip) versus \u003Cspan class=\"math-inline\">0.20 mm\u003C/span> between two planes (stripline), adding the upper ground plane increases capacitance per unit length and drops characteristic impedance by \u003Cstrong>\u003Cspan class=\"math-inline\">21.0 Ω\u003C/span>\u003C/strong>:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Topology (\u003Cspan class=\"math-inline\">h\u003Csub>nearest\u003C/sub> = 0.20 mm, ε\u003Csub>r\u003C/sub> = 3.66\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Trace Width (\u003Cspan class=\"math-inline\">W\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Calculated \u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub>\u003C/span>\u003C/th>\n\u003Cth align=\"right\">Effective Permittivity (\u003Cspan class=\"math-inline\">ε\u003Csub>eff\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth>Engineering Takeaway\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Surface Microstrip\u003C/strong> (\u003Cspan class=\"math-inline\">h = 0.20 mm\u003C/span>, air above)\u003C/td>\n\u003Ctd align=\"right\">\u003Cspan class=\"math-inline\">0.300 mm\u003C/span>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>62.4 Ω\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cspan class=\"math-inline\">2.768\u003C/span>\u003C/td>\n\u003Ctd>\u003Cspan class=\"math-inline\">12.4 Ω\u003C/span> above a \u003Cspan class=\"math-inline\">50 Ω\u003C/span> target; requires a wider conductor\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Centered Stripline\u003C/strong> (\u003Cspan class=\"math-inline\">B = 0.40 mm\u003C/span>, dual planes)\u003C/td>\n\u003Ctd align=\"right\">\u003Cspan class=\"math-inline\">0.300 mm\u003C/span>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>41.4 Ω\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cspan class=\"math-inline\">3.660\u003C/span>\u003C/td>\n\u003Ctd>\u003Cspan class=\"math-inline\">8.6 Ω\u003C/span> below a \u003Cspan class=\"math-inline\">50 Ω\u003C/span> target; requires a narrower conductor\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch3>Experiment 2: Synthesize Trace Width for a \u003Cspan class=\"math-inline\">50.0 Ω\u003C/span> Target\u003C/h3>\n\u003Cp>Solving both equations for \u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub> = 50.0 Ω\u003C/span> reveals the trade-off in conductor width and propagation delay (\u003Cspan class=\"math-inline\">t\u003Csub>pd\u003C/sub> = √ε\u003Csub>eff\u003C/sub>/c\u003C/span>):\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Topology (Sized for \u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub> = 50.0 Ω\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Required Trace Width (\u003Cspan class=\"math-inline\">W\u003Csub>50Ω\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Effective Permittivity (\u003Cspan class=\"math-inline\">ε\u003Csub>eff\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Propagation Delay (\u003Cspan class=\"math-inline\">t\u003Csub>pd\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Delay Over a \u003Cspan class=\"math-inline\">100 mm\u003C/span> Trace\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Surface Microstrip\u003C/strong> (\u003Cspan class=\"math-inline\">h = 0.20 mm\u003C/span>)\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.438 mm\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>2.858\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>5.64 ps/mm\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>564 ps\u003C/strong>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Centered Stripline\u003C/strong> (\u003Cspan class=\"math-inline\">B = 0.40 mm\u003C/span>)\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.218 mm\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>3.660\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>6.38 ps/mm\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>638 ps\u003C/strong> (\u003Cspan class=\"math-inline\">+74 ps\u003C/span> slower)\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Three practical layout conclusions jump directly out of these numbers:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Width & Copper Loss Tradeoff:\u003C/strong> At the same \u003Cspan class=\"math-inline\">0.20 mm\u003C/span> distance to the reference plane, the \u003Cspan class=\"math-inline\">50 Ω\u003C/span> stripline trace (\u003Cspan class=\"math-inline\">0.218 mm\u003C/span>) is roughly \u003Cstrong>half the width\u003C/strong> of the \u003Cspan class=\"math-inline\">50 Ω\u003C/span> microstrip trace (\u003Cspan class=\"math-inline\">0.438 mm\u003C/span>). While this lets you pack twice as many signals into an internal routing channel, the narrower stripline conductor has higher high-frequency skin-effect attenuation per unit length unless you increase the total dielectric thickness \u003Cspan class=\"math-inline\">B\u003C/span>.\u003C/li>\n\u003Cli>\u003Cstrong>Flight-Time Skew Across Layers:\u003C/strong> Over a \u003Cspan class=\"math-inline\">100 mm\u003C/span> route, the buried stripline signal arrives \u003Cstrong>\u003Cspan class=\"math-inline\">74 ps\u003C/span> later\u003C/strong> than the surface microstrip signal (\u003Cspan class=\"math-inline\">638 ps\u003C/span> vs. \u003Cspan class=\"math-inline\">564 ps\u003C/span>). On parallel DDR buses or length-matched clock trees that jump between outer and inner layers, always tune delay in \u003Cstrong>picoseconds (\u003Cspan class=\"math-inline\">t\u003Csub>pd\u003C/sub>\u003C/span>)\u003C/strong> rather than physical millimetres.\u003C/li>\n\u003Cli>\u003Cstrong>Why Production Stackups Require a 2D Field Solver:\u003C/strong> The closed-form \u003Cspan class=\"math-inline\">t=0\u003C/span> model isolates the fundamental topology shift, but a real manufactured PCB adds finite trapezoidal copper thickness (\u003Cspan class=\"math-inline\">t = 18--70 μm\u003C/span>), LPI solder mask over microstrip, copper surface roughness (\u003Cspan class=\"math-inline\">R\u003Csub>z\u003C/sub>\u003C/span>), and slightly different Dk values between laminated prepreg and core layers in offset/dual-stripline stacks. Never feed the microstrip output \u003Cspan class=\"math-inline\">ε\u003Csub>eff\u003C/sub> = 2.858\u003C/span> back into a 2D field solver's bulk substrate Dk input—supply the laminate's substrate Dk and let the solver compute geometry effects.\u003C/li>\n\u003C/ol>\n\u003Ch2>3. Evaluating the Whole Channel: Via Stubs, Return Paths, and Insertion Loss\u003C/h2>\n\u003Cp>A uniform transmission line segment is only half of the routing decision. Before moving a critical net from microstrip to stripline (or vice versa), evaluate the \u003Cstrong>complete point-to-point channel\u003C/strong>:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Short Surface RF & Microwave Launches (Favor Microstrip or Grounded Coplanar Waveguide):\u003C/strong> When connecting an RF transceiver IC directly to a top-side filter, power amplifier, and coaxial/antenna launch over \u003Cspan class=\"math-inline\">10--40 mm\u003C/span>, staying on Layer 1 eliminates two inductive via transitions and via stubs completely. Pulling solder mask back from the RF trace (solder-mask relief / windowing) eliminates solder-mask dielectric loss.\u003C/li>\n\u003Cli>\u003Cstrong>Dense Multi-Gigabit SerDes & Low-Jitter Clocks (Favor Stripline With Stub Control):\u003C/strong> On long differential channels (PCIe Gen 4/5/6, 25G/56G/112G Ethernet, DDR5) routed across congested boards, outer layers are blocked by component pads and suffer from FEXT and EMI radiation. Routing in internal stripline cavities between continuous \u003Ccode>GND\u003C/code> planes isolates the signals—provided you place \u003Cstrong>return-path ground stitching vias\u003C/strong> right next to every signal via transition and eliminate long PTH via stubs by routing on deep stripline layers (minimizing stub length) or specifying \u003Ca href=\"/en/blog/backdrill-pcb/\">controlled-depth backdrilling\u003C/a>.\u003C/li>\n\u003Cli>\u003Cstrong>Asymmetric / Offset Stripline & Dual Stripline:\u003C/strong> In high-layer-count boards, placing two signal layers between two reference planes (dual/offset stripline) saves plane layers, but couples the trace more strongly to the nearer plane (\u003Cspan class=\"math-inline\">h\u003Csub>1\u003C/sub> < h\u003Csub>2\u003C/sub>\u003C/span>). Route adjacent offset stripline layers orthogonally (or maintain \u003Cspan class=\"math-inline\">≥ 3W\u003C/span> broadside separation) to prevent broadside interlayer crosstalk.\u003C/li>\n\u003C/ul>\n\u003Ch2>4. Engineering Selection Matrix: When to Choose Microstrip vs. Stripline\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Design Constraint or Channel Requirement\u003C/th>\n\u003Cth>Recommended Structure\u003C/th>\n\u003Cth>Key Stackup & Layout Controls to Verify\u003C/th>\n\u003Cth>When to Reject or Modify This Choice\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Short RF front-end path requiring probe/tuning access and zero via discontinuities\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Uncoated Surface Microstrip\u003C/strong> (or Grounded Coplanar Waveguide)\u003C/td>\n\u003Ctd>Continuous L2 ground plane underneath; specify solder-mask keepout over RF trace; use ENIG/Immersion Ag finish\u003C/td>\n\u003Ctd>Reject if dense top-side component placement forces multiple layer jumps or close parallel aggressor routing\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>High-density SerDes, clock, or parallel bus requiring low FEXT and EMI containment\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Symmetric or Offset Stripline\u003C/strong>\u003C/td>\n\u003Ctd>Continuous upper and lower reference planes; place GND stitching vias within \u003Cspan class=\"math-inline\"><1--2 mm\u003C/span> of every signal via transition\u003C/td>\n\u003Ctd>Reject or add \u003Cstrong>backdrilling / blind microvias\u003C/strong> if residual PTH via stub length exceeds \u003Cspan class=\"math-inline\">~ λ / (4--10)\u003C/span> at the Nyquist/harmonic bandwidth\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Cost-constrained 4-layer board (\u003Ccode>Sig-GND-PWR-Sig\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Coated Outer Microstrip\u003C/strong> on L1 and L4\u003C/td>\n\u003Ctd>Keep L1 referenced to L2 \u003Ccode>GND\u003C/code>; if L4 references L3 \u003Ccode>PWR\u003C/code>, place high-frequency decoupling capacitors at via transitions\u003C/td>\n\u003Ctd>Avoid routing high-speed differential pairs across splits in the L3 power plane without continuous return reference\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Long backplane or server motherboard link with tight insertion-loss budget (\u003Cspan class=\"math-inline\">S\u003Csub>21\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Wide-Conducted Stripline\u003C/strong> in low-loss laminate (e.g., Megtron 6 / Isola / Rogers)\u003C/td>\n\u003Ctd>Use thicker dielectric spacing \u003Cspan class=\"math-inline\">B\u003C/span> so \u003Cspan class=\"math-inline\">50 Ω / 100 Ω\u003C/span> traces stay wide enough (\u003Cspan class=\"math-inline\">0.18--0.25 mm\u003C/span>) to minimize copper skin loss; specify HVLP/VLP foil\u003C/td>\n\u003Ctd>Do not assume stripline has lower total loss than microstrip if thin prepreg forces ultra-narrow (\u003Cspan class=\"math-inline\">0.09 mm\u003C/span>) high-resistance inner traces\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>5. Handing Off Your Stackup and Controlled-Impedance Table for Fabrication\u003C/h2>\n\u003Cp>Once your topology and layer assignments are selected, lock the fabrication specification using our \u003Ca href=\"/en/blog/controlled-impedance-pcb-design-review/\">controlled-impedance PCB design review checklist\u003C/a>. When submitting your \u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing\u003C/a> RFQ, include:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Proposed Layer Stackup & Material Grade:\u003C/strong> Specifying core/prepreg thicknesses, copper weights (including plated outer copper vs. inner foil), and target laminate family (standard high-\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span> FR-4, mid-loss, low-loss, or hybrid RF).\u003C/li>\n\u003Cli>\u003Cstrong>Complete Impedance Summary Table:\u003C/strong> Listing every controlled layer, topology (\u003Ccode>Coated Microstrip\u003C/code>, \u003Ccode>Uncoated Microstrip\u003C/code>, \u003Ccode>Symmetric Stripline\u003C/code>, \u003Ccode>Offset Stripline\u003C/code>, \u003Ccode>Coplanar\u003C/code>), single-ended or differential target (\u003Cspan class=\"math-inline\">Ω ± %\u003C/span>), reference plane layer numbers, and CAD trace width/spacing.\u003C/li>\n\u003Cli>\u003Cstrong>Allowed CAM Trace-Width Adjustment Window:\u003C/strong> State whether the fabricator's CAM team may adjust controlled-impedance trace widths by \u003Cspan class=\"math-inline\">± 10--15%\u003C/span> to match exact pressed prepreg thicknesses and etch factors, or must submit a stackup EQ before altering copper widths.\u003C/li>\n\u003C/ol>\n\u003Cp>HILPCB's signal-integrity and CAM engineering team models every \u003Ca href=\"/en/products/multilayer-pcb/\">multilayer PCB\u003C/a>, \u003Ca href=\"/en/products/high-speed-pcb/\">high-speed PCB\u003C/a>, and \u003Ca href=\"/en/products/rogers-pcb/\">Rogers RF PCB\u003C/a> stackup using 2D field solvers correlated to production press-out data—delivering \u003Cstrong>±5% TDR impedance control\u003C/strong>, \u003Cstrong>controlled-depth backdrilling (residual stubs \u003Cspan class=\"math-inline\"><10 mil\u003C/span>)\u003C/strong>, and sample VNA testing up to \u003Cstrong>40 GHz\u003C/strong>. Upload your Gerber/ODB++ files and stackup table when you \u003Ca href=\"/en/quote/\">request a quote\u003C/a> for an engineering impedance review.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>Why is a 50 Ω stripline trace narrower than a 50 Ω microstrip trace at the same dielectric distance?\u003C/h3>\n\u003Cp>Characteristic impedance is inversely proportional to capacitance per unit length (\u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub> = √L/C\u003C/span>). Because a stripline conductor is coupled to \u003Cstrong>two\u003C/strong> reference planes (above and below) inside a higher-permittivity dielectric rather than one plane with air above, it has significantly higher capacitance for a given width. To bring capacitance back down and restore \u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub> = 50 Ω\u003C/span>, the stripline conductor must be made narrower (or the dielectric spacing between planes must be increased).\u003C/p>\n\u003Ch3>Why does microstrip have higher far-end crosstalk (FEXT) than symmetric stripline?\u003C/h3>\n\u003Cp>In a homogeneous stripline medium, the electric (capacitive) and magnetic (inductive) coupling ratios between two adjacent traces are equal, so odd-mode and even-mode signals travel at the exact same phase velocity (\u003Cspan class=\"math-inline\">v\u003Csub>odd\u003C/sub> = v\u003Csub>even\u003C/sub>\u003C/span>) and far-end crosstalk cancels out theoretically. In surface microstrip, electric field lines fringe into the air above the board; odd-mode fields have a higher fraction of energy in air than even-mode fields, causing velocity mismatch (\u003Cspan class=\"math-inline\">v\u003Csub>odd\u003C/sub> > v\u003Csub>even\u003C/sub>\u003C/span>) that produces a large FEXT pulse at the receiver.\u003C/p>\n\u003Ch3>How much does solder mask change the impedance of an outer-layer microstrip trace?\u003C/h3>\n\u003Cp>Applying standard liquid photoimageable (LPI) solder mask (\u003Cspan class=\"math-inline\">15--30 μm\u003C/span> thick, \u003Cspan class=\"math-inline\">ε\u003Csub>r\u003C/sub> ≈ 3.3--3.8\u003C/span>) over an outer-layer microstrip trace replaces the air interface directly above the conductor with a higher-permittivity dielectric. This typically lowers single-ended characteristic impedance by \u003Cstrong>\u003Cspan class=\"math-inline\">2 to 3 Ω\u003C/span>\u003C/strong> (and differential impedance by \u003Cstrong>\u003Cspan class=\"math-inline\">3 to 5 Ω\u003C/span>\u003C/strong>), which must be included in the 2D field-solver model before sizing the trace width.\u003C/p>\n\u003Ch3>When does stripline perform worse than microstrip at high frequencies?\u003C/h3>\n\u003Cp>Stripline can degrade a high-frequency channel in two situations: (1) when transitions from top-layer SMD pads into shallow internal stripline layers leave \u003Cstrong>long through-hole via stubs\u003C/strong> whose quarter-wave resonance notches out the signal spectrum, and (2) when a tight layer-count stackup forces stripline into ultra-thin dielectrics (\u003Cspan class=\"math-inline\"><0.08 mm\u003C/span>), requiring narrow traces (\u003Cspan class=\"math-inline\"><0.10 mm\u003C/span>) whose skin-effect and copper-roughness conductor loss exceeds the dielectric loss savings.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/material-data-sheet-reading-pcb-stackup-materials/\">PCB material data sheet reading: 20 stackup and material FAQs engineers should know\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/microstrip-vs-stripline/calculate.py\">calculate.py\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/microstrip-vs-stripline/calculated-results.csv\">calculated-results.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/microstrip-vs-stripline/README.md\">formula notes\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/backdrill-pcb/\">Backdrill PCB: Removing Via Stubs for High-Speed Signal Integrity\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/controlled-impedance-pcb-design-review/\">Controlled Impedance PCB Design Review Before Fabrication Release\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,18,21,25],{"question":15,"answer":16,"answerText":17},"Why is a 50 Ω stripline trace narrower than a 50 Ω microstrip trace at the same dielectric distance?","Characteristic impedance is inversely proportional to capacitance per unit length ($Z_0 = \\sqrt{L/C}$). Because a stripline conductor is coupled to **two** reference planes (above and below) inside a higher-permittivity dielectric rather than one plane with air above, it has significantly higher capacitance for a given width. To bring capacitance back down and restore $Z_0 = 50\\ \\Omega$, the stripline conductor must be made narrower (or the dielectric spacing between planes must be increased).","Characteristic impedance is inversely proportional to capacitance per unit length ($Z_0 = \\sqrt{L/C}$). Because a stripline conductor is coupled to two reference planes (above and below) inside a higher-permittivity dielectric rather than one plane with air above, it has significantly higher capacitance for a given width. To bring capacitance back down and restore $Z_0 = 50\\ \\Omega$, the stripline conductor must be made narrower (or the dielectric spacing between planes must be increased).",{"question":19,"answer":20,"answerText":20},"Why does microstrip have higher far-end crosstalk (FEXT) than symmetric stripline?","In a homogeneous stripline medium, the electric (capacitive) and magnetic (inductive) coupling ratios between two adjacent traces are equal, so odd-mode and even-mode signals travel at the exact same phase velocity ($v_{\\text{odd}} = v_{\\text{even}}$) and far-end crosstalk cancels out theoretically. In surface microstrip, electric field lines fringe into the air above the board; odd-mode fields have a higher fraction of energy in air than even-mode fields, causing velocity mismatch ($v_{\\text{odd}} > v_{\\text{even}}$) that produces a large FEXT pulse at the receiver.",{"question":22,"answer":23,"answerText":24},"How much does solder mask change the impedance of an outer-layer microstrip trace?","Applying standard liquid photoimageable (LPI) solder mask ($15\\text{--}30\\ \\mu\\text{m}$ thick, $\\varepsilon_r \\approx 3.3\\text{--}3.8$) over an outer-layer microstrip trace replaces the air interface directly above the conductor with a higher-permittivity dielectric. This typically lowers single-ended characteristic impedance by **$2\\text{ to }3\\ \\Omega$** (and differential impedance by **$3\\text{ to }5\\ \\Omega$**), which must be included in the 2D field-solver model before sizing the trace width.","Applying standard liquid photoimageable (LPI) solder mask ($15\\text{--}30\\ \\mu\\text{m}$ thick, $\\varepsilon_r \\approx 3.3\\text{--}3.8$) over an outer-layer microstrip trace replaces the air interface directly above the conductor with a higher-permittivity dielectric. This typically lowers single-ended characteristic impedance by $2\\text{ to }3\\ \\Omega$ (and differential impedance by $3\\text{ to }5\\ \\Omega$), which must be included in the 2D field-solver model before sizing the trace width.",{"question":26,"answer":27,"answerText":28},"When does stripline perform worse than microstrip at high frequencies?","Stripline can degrade a high-frequency channel in two situations: (1) when transitions from top-layer SMD pads into shallow internal stripline layers leave **long through-hole via stubs** whose quarter-wave resonance notches out the signal spectrum, and (2) when a tight layer-count stackup forces stripline into ultra-thin dielectrics ($\u003C0.08\\text{ mm}$), requiring narrow traces ($\u003C0.10\\text{ mm}$) whose skin-effect and copper-roughness conductor loss exceeds the dielectric loss savings.","Stripline can degrade a high-frequency channel in two situations: (1) when transitions from top-layer SMD pads into shallow internal stripline layers leave long through-hole via stubs whose quarter-wave resonance notches out the signal spectrum, and (2) when a tight layer-count stackup forces stripline into ultra-thin dielectrics ($\u003C0.08\\text{ mm}$), requiring narrow traces ($\u003C0.10\\text{ mm}$) whose skin-effect and copper-roughness conductor loss exceeds the dielectric loss savings.",[30,31,32,33],"microstrip vs stripline","PCB transmission line","controlled impedance","high-speed PCB routing","microstrip-vs-stripline","en",[35,37,38,39,40],"de","cn","fr","ru",{"blog":42,"breadcrumb":51},{"@context":43,"@type":44,"headline":4,"description":5,"image":8,"url":45,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":46,"articleSection":7,"author":47,"publisher":50},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/microstrip-vs-stripline/","microstrip vs stripline, PCB transmission line, controlled impedance, high-speed PCB routing",{"@type":48,"name":49},"Organization","HILPCB",{"@type":48,"name":49},{"@context":43,"@type":52,"itemListElement":53},"BreadcrumbList",[54,59,63],{"@type":55,"position":56,"name":57,"item":58},"ListItem",1,"Home","https://hilpcb.com/",{"@type":55,"position":60,"name":61,"item":62},2,"Blog","https://hilpcb.com/en/blog/",{"@type":55,"position":64,"name":34,"item":45},3,1793496913342]