[{"data":1,"prerenderedAt":48},["ShallowReactive",2],{"blog-pcb-delamination-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":14,"slug":22,"sourceLocale":23,"jsonld":24},"PCB Delamination: Causes, Measling vs Blistering, IPC-A-600 Acceptance, and How to Prevent It","PCB delamination explained: delamination meaning, measling vs blistering and haloing, root causes, IPC-A-600 Class 1/2/3 acceptance criteria, and prevention.","2025-10-10","technology","/assets/img/blogs/multilayer-fr4-pcb.webp",12,2305,"PT12M","\u003Cp>\u003Cstrong>PCB delamination\u003C/strong> is a laminate defect in which the internal layers of a printed circuit board — copper foil, prepreg, and core substrate — separate from each other, or copper lifts away from the base material. It is usually triggered by thermal stress, absorbed moisture, or material and lamination process problems. Whether a delaminated area is acceptable or a reject is judged against the product's IPC-A-600 class, which is why understanding this defect matters to designers, inspectors, and buyers alike.\u003C/p>\n\u003Cp>This guide answers \u003Cstrong>what is delamination\u003C/strong> in practical terms, distinguishes it from the visually similar defects measling, blistering, and haloing, explains root causes, and shows how to prevent it and when to reject a board.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2>What Is Delamination? Meaning and Visual Forms\u003C/h2>\n\u003Cp>The general \u003Cstrong>delamination meaning\u003C/strong> is the separation of bonded layers in any laminated material — from plywood to composites to steel cladding. In electronics, \u003Cstrong>circuit board delamination\u003C/strong> refers specifically to separation inside a PCB: between copper and resin, between prepreg and core, or between inner copper layers of a multilayer stackup. Because a PCB is a bonded composite of copper and glass-reinforced resin, any weakness at those interfaces can open into a gap under stress.\u003C/p>\n\u003Cp>IPC-A-600, the acceptability standard for bare printed boards, groups four visually related laminate conditions that inspectors must tell apart:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Condition\u003C/th>\n\u003Cth>Definition\u003C/th>\n\u003Cth>Visual Appearance\u003C/th>\n\u003Cth>Typical Location\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Delamination\u003C/strong>\u003C/td>\n\u003Ctd>Actual separation between laminate layers, or between copper and base material\u003C/td>\n\u003Ctd>Visible gap, lifted foil, or a raised region confirmed by cross-section\u003C/td>\n\u003Ctd>Layer interfaces, often near plated holes or board edges\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Measling\u003C/strong>\u003C/td>\n\u003Ctd>Small white spots in the glass weave where resin has separated from glass bundles at the weave crossover points\u003C/td>\n\u003Ctd>Discrete white dots inside the laminate, below the surface\u003C/td>\n\u003Ctd>Within the woven glass layers of FR-4\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Blistering\u003C/strong>\u003C/td>\n\u003Ctd>A localized surface swelling and separation between any layers of the base material or between the laminate and a surface coating\u003C/td>\n\u003Ctd>Raised dome or bubble on the surface, sometimes over solder mask\u003C/td>\n\u003Ctd>Surface layers, often after soldering heat\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Haloing\u003C/strong>\u003C/td>\n\u003Ctd>A ring of mechanically fractured or whitened laminate around a drilled hole, without full layer separation\u003C/td>\n\u003Ctd>Pale ring centered on a drilled hole\u003C/td>\n\u003Ctd>Annular ring zone around holes\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The distinction matters because the acceptance limits differ: measling and haloing are often cosmetic conditions with defined size and distance criteria, while true delamination — an open separation between functional layers — is treated far more strictly. When engineers search for \u003Cstrong>PCB delamination images\u003C/strong>, what they usually find is a mix of all four conditions; correct identification is the first step before any accept/reject decision can be made.\u003C/p>\n\u003Cp>A quick field rule: if the white or raised feature sits \u003Cem>within\u003C/em> the glass weave without an actual gap, suspect measling; if there is a real separation plane between layers, it is delamination. Cross-section microsectioning is the definitive way to confirm which condition you are looking at.\u003C/p>\n\u003Ch2>What Causes PCB Delamination?\u003C/h2>\n\u003Cp>The \u003Cstrong>delamination of PCB\u003C/strong> laminates almost never has a single cause. It is the result of adhesion margin at a layer interface being exceeded by stress. The root causes fall into three families:\u003C/p>\n\u003Ch3>Material Causes\u003C/h3>\n\u003Cul>\n\u003Cli>\u003Cstrong>Low or marginal Tg\u003C/strong>: Standard FR-4 softens above its glass transition temperature; boards exposed to lead-free reflow peaks with a low-Tg laminate lose resin strength exactly when thermal stress peaks.\u003C/li>\n\u003Cli>\u003Cstrong>CTE mismatch\u003C/strong>: Copper, glass, and resin expand at different rates, especially in the Z-axis through the board thickness. Thick multilayer boards accumulate large Z-axis expansion during reflow.\u003C/li>\n\u003Cli>\u003Cstrong>Glass weave and resin quality\u003C/strong>: Poor resin wet-out of the glass bundle, voids in the prepreg, or inconsistent resin content leave weak interfaces that later open as measling or delamination.\u003C/li>\n\u003Cli>\u003Cstrong>Moisture-absorbing laminates\u003C/strong>: Hygroscopic resin systems raise the risk of steam-driven separation when the board is heated.\u003C/li>\n\u003C/ul>\n\u003Ch3>Process Causes\u003C/h3>\n\u003Cul>\n\u003Cli>\u003Cstrong>Lamination profile errors\u003C/strong>: Insufficient pressure, incorrect heating ramp, or under-cured resin during multilayer pressing leaves weak interlayer bonds from day one.\u003C/li>\n\u003Cli>\u003Cstrong>Drilling smear and poor desmear\u003C/strong>: Resin smear left on inner-layer copper after drilling, or an over/under-aggressive desmear process, weakens the copper-to-laminate bond around holes.\u003C/li>\n\u003Cli>\u003Cstrong>Contamination before pressing\u003C/strong>: Oxide, fingerprints, or moisture on inner layers or copper foil prevent proper bonding.\u003C/li>\n\u003Cli>\u003Cstrong>Plating stress\u003C/strong>: Excessive stress in electroless or electrolytic copper deposits can pull the copper away from the hole wall or surface.\u003C/li>\n\u003C/ul>\n\u003Ch3>Environmental and Assembly Causes\u003C/h3>\n\u003Cul>\n\u003Cli>\u003Cstrong>Moisture uptake before soldering\u003C/strong>: A board that has absorbed moisture and is not baked before reflow can develop steam pressure at layer interfaces — the classic "popcorning" mechanism behind blistering and delamination.\u003C/li>\n\u003Cli>\u003Cstrong>Thermal shock and repeated reflow\u003C/strong>: Rapid temperature swings, multiple reflow cycles, rework, and wave soldering all add cumulative thermal stress.\u003C/li>\n\u003Cli>\u003Cstrong>Field environment\u003C/strong>: High-humidity service and thermal cycling in the application continue to stress weak interfaces after delivery.\u003C/li>\n\u003C/ul>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Root Cause\u003C/th>\n\u003Cth>Visible Symptom\u003C/th>\n\u003Cth>Trigger\u003C/th>\n\u003Cth>Process Stage\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Low Tg laminate on a lead-free profile\u003C/td>\n\u003Ctd>Delamination near holes after reflow\u003C/td>\n\u003Ctd>Reflow peak above laminate capability\u003C/td>\n\u003Ctd>Material selection\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Moisture absorbed before reflow\u003C/td>\n\u003Ctd>Blistering, delamination domes\u003C/td>\n\u003Ctd>Steam expansion during soldering\u003C/td>\n\u003Ctd>Storage / pre-bake\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Under-cured lamination\u003C/td>\n\u003Ctd>Widespread measling, layer gaps\u003C/td>\n\u003Ctd>Normal handling and soldering heat\u003C/td>\n\u003Ctd>Multilayer pressing\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Drill smear / weak desmear\u003C/td>\n\u003Ctd>Hole-wall separation, inner-layer delamination\u003C/td>\n\u003Ctd>Thermal stress test or reflow\u003C/td>\n\u003Ctd>Drilling / plating\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Repeated rework cycles\u003C/td>\n\u003Ctd>Local delamination around reworked pads\u003C/td>\n\u003Ctd>Localized high heat\u003C/td>\n\u003Ctd>Assembly / rework\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>One related failure mechanism deserves a mention: \u003Cstrong>conductive anodic filament (CAF)\u003C/strong> growth is an electrochemical failure where copper salts grow along the glass-resin interface under bias and humidity. CAF is not delamination — it causes leakage and shorts rather than mechanical separation — but both failures exploit the same weak glass-resin interface, so laminates and processes that resist one generally resist the other.\u003C/p>\n\u003Ch2>IPC-A-600 Acceptance Criteria for Delamination, Measling and Blistering\u003C/h2>\n\u003Cp>\u003Cstrong>IPC-A-600 (Acceptability of Printed Boards)\u003C/strong> is the visual inspection standard that tells a bare-board inspector whether a laminate condition is a target condition, acceptable, or nonconforming for the board's specified class. IPC-6012, the companion performance specification for rigid boards, sets the qualification and test requirements — including thermal stress survival and microsection evaluation — that the board must meet before visual acceptance is even discussed.\u003C/p>\n\u003Cp>The acceptance decision for any of the four laminate conditions follows this framework:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Defect\u003C/th>\n\u003Cth>IPC Class 1 (General Electronics)\u003C/th>\n\u003Cth>IPC Class 2 (Dedicated Service)\u003C/th>\n\u003Cth>IPC Class 3 (High Reliability)\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Measling\u003C/strong>\u003C/td>\n\u003Ctd>Acceptable within defined size and area limits; nonconforming when it bridges conductor spacing below the minimum allowed\u003C/td>\n\u003Ctd>Tighter size/area limits than Class 1; must not reduce conductor spacing below minimum\u003C/td>\n\u003Ctd>Most restrictive limits; essentially cosmetic-only allowance\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Blistering\u003C/strong>\u003C/td>\n\u003Ctd>Acceptable only within defined size limits and where it does not reduce conductor spacing or compromise plated holes\u003C/td>\n\u003Ctd>More restrictive; any blister affecting holes or spacing is nonconforming\u003C/td>\n\u003Ctd>Effectively reject; surface separation is not tolerated\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Haloing\u003C/strong>\u003C/td>\n\u003Ctd>Acceptable within a defined ring width around the hole\u003C/td>\n\u003Ctd>Tighter allowable ring width\u003C/td>\n\u003Ctd>Tightest allowable ring width\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Delamination\u003C/strong>\u003C/td>\n\u003Ctd>Any true layer separation is generally nonconforming regardless of class; class affects only how borderline conditions are dispositioned\u003C/td>\n\u003Ctd>Reject\u003C/td>\n\u003Ctd>Reject\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Read the table as a decision framework, not as numeric law: the exact size, area-percentage, and spacing figures for each condition are defined in the current IPC-A-600 revision, and your purchase agreement should state which revision and class apply. What the framework gives you is the disposition logic:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Identify the condition first\u003C/strong> (the previous section) — acceptance limits differ by defect type.\u003C/li>\n\u003Cli>\u003Cstrong>Check the board's contracted class\u003C/strong> — the same measling pattern can pass Class 1 and fail Class 3.\u003C/li>\n\u003Cli>\u003Cstrong>Check the functional consequence\u003C/strong> — any condition that reduces conductor spacing below the minimum, bridges conductors, or affects a plated hole is nonconforming in every class.\u003C/li>\n\u003Cli>\u003Cstrong>When in doubt, microsection\u003C/strong> — IPC-6012 thermal stress coupons and microsection analysis give objective evidence of whether an apparent surface defect is a true interlayer separation.\u003C/li>\n\u003C/ol>\n\u003Cp>For the full hierarchy of where IPC-A-600 and IPC-6012 sit among design, material, and assembly standards, see our \u003Ca href=\"/en/blog/ipc-standards-for-pcbs/\">IPC standards for PCBs guide\u003C/a> and the \u003Ca href=\"/en/blog/ipc-standards-mastery/\">IPC standards mastery overview\u003C/a>.\u003C/p>\n\u003Ch2>How to Prevent PCB Delamination in Fabrication and Assembly\u003C/h2>\n\u003Cp>Prevention works on both sides of the interface: choose materials with enough margin, then protect that margin through fabrication and assembly.\u003C/p>\n\u003Cp>\u003Cstrong>Material selection:\u003C/strong>\u003C/p>\n\u003Cul>\n\u003Cli>Specify a laminate Tg appropriate to the assembly profile — for lead-free reflow, that typically means moving beyond standard-Tg FR-4, as covered in our \u003Ca href=\"/en/blog/high-tg-pcb/\">high-TG PCB guide\u003C/a>.\u003C/li>\n\u003Cli>For thick multilayer boards, evaluate Z-axis CTE and decomposition temperature (Td), not just Tg.\u003C/li>\n\u003Cli>Use laminates from qualified manufacturers with controlled resin content and glass wet-out.\u003C/li>\n\u003C/ul>\n\u003Cp>\u003Cstrong>Fabrication controls:\u003C/strong>\u003C/p>\n\u003Cul>\n\u003Cli>Validate the lamination press cycle (temperature ramp, pressure, cure time) for each stackup, and control inner-layer cleanliness and oxide treatment before pressing.\u003C/li>\n\u003Cli>Control drilling parameters and the desmear process so hole walls bond reliably to plating.\u003C/li>\n\u003Cli>Bake moisture-sensitive laminates and prepregs within their specified floor life.\u003C/li>\n\u003C/ul>\n\u003Cp>\u003Cstrong>Assembly and handling controls:\u003C/strong>\u003C/p>\n\u003Cul>\n\u003Cli>Store bare boards in moisture barrier bags and bake boards that have exceeded their floor life before reflow — the same moisture-management discipline defined for components applies to bare boards.\u003C/li>\n\u003Cli>Minimize rework cycles and control localized rework heat.\u003C/li>\n\u003Cli>Verify process capability with thermal stress testing (solder float or reflow simulation coupons per IPC-TM-650 methods) and, for internal defects that visual inspection cannot see, scanning acoustic microscopy (SAM) on a sample basis. Our \u003Ca href=\"/en/blog/thermal-cycling-testing/\">thermal cycling testing guide\u003C/a> explains how accelerated cycling exposes weak interfaces before product release.\u003C/li>\n\u003C/ul>\n\u003Ch2>When Should You Reject a Board and Request a Refab?\u003C/h2>\n\u003Cp>Reject the lot — do not sort silently — when any of these conditions hold:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Confirmed delamination\u003C/strong> on microsection or cross-section, at any class. An open layer separation is a latent reliability failure: it propagates under thermal cycling and can sever plated hole barrels.\u003C/li>\n\u003Cli>\u003Cstrong>Measling or haloing beyond the class limits\u003C/strong> in the contracted IPC-A-600 revision, or any instance that reduces conductor spacing below the minimum.\u003C/li>\n\u003Cli>\u003Cstrong>Blistering over plated holes or conductor spacing\u003C/strong> in Class 2/3 product.\u003C/li>\n\u003Cli>\u003Cstrong>Thermal stress coupon failure\u003C/strong> in the qualification microsection, even if production boards look acceptable.\u003C/li>\n\u003C/ul>\n\u003Cp>When rejecting, build the negotiation on evidence rather than opinion:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Document with the standard\u003C/strong>: cite the defect type, the contracted IPC-A-600 class and revision, and photographs or microsection images.\u003C/li>\n\u003Cli>\u003Cstrong>Provide objective test data\u003C/strong>: thermal stress coupon results, SAM scans, or cross-sections are far harder to dispute than visual impressions.\u003C/li>\n\u003Cli>\u003Cstrong>Agree the disposition\u003C/strong>: refab, rework (rarely viable for true delamination), or a documented concession for cosmetic-only conditions such as in-spec measling.\u003C/li>\n\u003Cli>\u003Cstrong>Fix the root cause upstream\u003C/strong>: a refab without a lamination, material, or moisture-control corrective action will repeat the failure.\u003C/li>\n\u003C/ol>\n\u003Cp>A capable manufacturer will already run these controls. When evaluating suppliers, ask for their lamination process controls, microsection reports, thermal stress test data, and moisture management procedure — the same evidence you would use to reject a bad lot is the evidence a good factory produces routinely.\u003C/p>\n\u003Chr>\n\u003Ch2>Frequently Asked Questions (FAQ)\u003C/h2>\n\u003Ch3>What is delamination in a PCB?\u003C/h3>\n\u003Cp>Delamination in a PCB is the physical separation of bonded layers — copper from resin, prepreg from core, or inner layers from each other — caused by thermal stress, moisture, or weak interlayer bonding from material or lamination problems. It is treated as a serious, generally nonconforming defect under IPC-A-600.\u003C/p>\n\u003Ch3>What is the difference between measling and blistering?\u003C/h3>\n\u003Cp>Measling is a subsurface condition: small white spots in the glass weave where resin has separated from glass bundles at weave crossover points. Blistering is a surface condition: a raised, localized swelling where surface layers or a coating have separated. Measling is often cosmetic and acceptable within class limits; blistering is judged more strictly, especially near plated holes.\u003C/p>\n\u003Ch3>What causes PCB delamination?\u003C/h3>\n\u003Cp>The main causes are moisture absorbed before reflow (steam expansion at layer interfaces), thermal stress exceeding a low-Tg laminate's capability, lamination process errors such as under-cure or contamination, drilling smear and weak desmear, and repeated rework or thermal cycling.\u003C/p>\n\u003Ch3>Can a delaminated PCB be repaired?\u003C/h3>\n\u003Cp>Generally no. True delamination is a separation inside the laminate that cannot be reliably rebonded, and repair attempts leave latent reliability risk. Cosmetic conditions such as in-spec measling may be accepted or conceded, but a board with confirmed interlayer separation should be refabricated.\u003C/p>\n\u003Ch3>What does IPC-A-600 say about delamination?\u003C/h3>\n\u003Cp>IPC-A-600 treats true delamination — an actual separation between layers or between copper and base material — as nonconforming for all classes, while measling, blistering, and haloing have class-dependent size and area acceptance limits. The exact dimensional criteria are defined in the current revision of the standard, which your purchase agreement should reference explicitly.\u003C/p>\n\u003Chr>\n\u003Ch2>Build Reliable Boards with HILPCB\u003C/h2>\n\u003Cp>HILPCB controls every factor that drives PCB delamination — qualified laminates, validated lamination press cycles, controlled drilling and desmear, moisture management, and thermal stress verification with microsection evidence on every lot:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Material Control\u003C/strong>: High-TG and low-CTE laminate options matched to your lead-free assembly profile.\u003C/li>\n\u003Cli>\u003Cstrong>Process Verification\u003C/strong>: IPC-A-600 visual acceptance and IPC-6012 thermal stress coupon testing with documented microsection reports.\u003C/li>\n\u003Cli>\u003Cstrong>Full Traceability\u003C/strong>: Lot-level records from laminate batch through final electrical test.\u003C/li>\n\u003C/ul>\n\u003Cp>Upload your Gerber files to our \u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing service\u003C/a> for a free DFM review and a quote backed by verifiable quality evidence — or start with our \u003Ca href=\"/en/blog/circuit-board/\">circuit board fundamentals guide\u003C/a> if you are still mapping the landscape.\u003C/p>\n\u003Cp>Specifying high-Tg laminates with matched CTE in a \u003Ca href=\"/en/blog/custom-pcb/\">custom printed circuit board\u003C/a> significantly mitigates z-axis thermal expansion stresses during multi-cycle reflow.\u003C/p>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/ipc-standards-for-pcbs/\">IPC Standards for PCBs: What IPC Means, Key Standards Hierarchy, and Classes Explained\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/ipc-standards-mastery/\">IPC Standards Mastery: Understanding A-610 vs J-STD-001 Requirements\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/high-tg-pcb/\">High-Tg PCB Manufacturing: Advanced Thermal Performance Circuit Boards\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/thermal-cycling-testing/\">PCB Thermal Cycling Testing: Advanced Reliability Validation\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing service\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/circuit-board/\">Circuit Board Manufacturing: Complete PCB Production Process Guide 2025\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/custom-pcb/\">Custom PCB Manufacturing for Complex Designs and Special Materials\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[],[15,16,17,18,19,20,21],"PCB Delamination","Delamination","Measling","Blistering","IPC-A-600","PCB Quality","PCB Manufacturing","pcb-delamination","en",{"blog":25,"breadcrumb":34},{"@context":26,"@type":27,"headline":4,"description":5,"image":8,"url":28,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":29,"articleSection":7,"author":30,"publisher":33},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pcb-delamination/","PCB Delamination, Delamination, Measling, Blistering, IPC-A-600, PCB Quality, PCB Manufacturing",{"@type":31,"name":32},"Organization","HILPCB",{"@type":31,"name":32},{"@context":26,"@type":35,"itemListElement":36},"BreadcrumbList",[37,42,46],{"@type":38,"position":39,"name":40,"item":41},"ListItem",1,"Home","https://hilpcb.com/",{"@type":38,"position":43,"name":44,"item":45},2,"Blog","https://hilpcb.com/en/blog/",{"@type":38,"position":47,"name":22,"item":28},3,1791623033512]