[{"data":1,"prerenderedAt":51},["ShallowReactive",2],{"blog-pcb-layout-guide-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":14,"slug":25,"sourceLocale":26,"jsonld":27},"PCB Layout Guide: Placement, Routing and Layout Rules","Comprehensive engineering guide to PCB layout design: component floorplanning, routing techniques, stackup constraints, high-speed rules, and DFM best practices.","2025-10-10","technology","/assets/img/blogs/circuit-board.webp",11,2083,"PT11M","\u003Cp>Printed circuit board layout is the rigorous engineering discipline that translates an abstract schematic circuit into a physical, manufacturable board geometry. More than merely connecting logical netlist nodes with copper tracks, \u003Cstrong>PCB layout design\u003C/strong> governs signal integrity, electromagnetic compatibility (EMC), thermal dissipation, power distribution network (PDN) impedance, and manufacturing yields.\u003C/p>\n\u003Cp>Flawed layout decisions—such as routing high-speed differential pairs across split reference planes, placing decoupling capacitors far from IC power pins, or neglecting trace width ampacity limits—lead to intermittent hardware failures, radiated emission test failures, and costly fabrication respins. This comprehensive engineering guide details core \u003Cstrong>PCB layout rules\u003C/strong>, establishes floorplanning best practices for \u003Cstrong>component placement\u003C/strong>, covers advanced \u003Cstrong>routing techniques\u003C/strong>, and outlines actionable design guidelines for mixed-signal, RF, and power circuitry.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003Ch2>What Is PCB Layout?\u003C/h2>\n\u003Cp>\u003Cstrong>PCB layout\u003C/strong> is the phase of electronic product development where logical components and connectivity from a schematic capture tool are instantiated as real three-dimensional physical entities. The designer defines board outlines, layer stackups, component footprints, routing topologies, via structures, and copper pour regions within computer-aided design (EDA) software such as Altium Designer, Cadence Allegro, Siemens Xpedition, or KiCad.\u003C/p>\n\u003Cp>The standard PCB layout workflow proceeds through five sequential engineering phases:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Mechanical & Form Factor Definition\u003C/strong>: Importing CAD outlines (DXF or STEP models), defining mounting hole locations, keepout zones, height restrictions, and board edge clearances.\u003C/li>\n\u003Cli>\u003Cstrong>Layer Stackup Configuration\u003C/strong>: Defining copper foil thicknesses, dielectric core and prepreg materials, and target single-ended (typically 50 $\\Omega$) and differential (typically 90 $\\Omega$ or 100 $\\Omega$) controlled impedance profiles based on \u003Ca href=\"/en/blog/pcb-materials-guide/\">PCB substrate materials\u003C/a>.\u003C/li>\n\u003Cli>\u003Cstrong>Component Floorplanning & Placement\u003C/strong>: Positioning functional circuit blocks, aligning critical connectors and thermal sinks, and placing bypass and decoupling components.\u003C/li>\n\u003Cli>\u003Cstrong>Signal and Power Routing\u003C/strong>: Escaping dense IC packages, routing critical clock and high-speed traces, routing power buses, and flooding continuous ground planes.\u003C/li>\n\u003Cli>\u003Cstrong>Design Rule Verification & Manufacturing Output\u003C/strong>: Executing automated Design Rule Checks (DRC), performing Design for Manufacturing (DFM) audits, and generating fabrication artwork (ODB++, Gerber X2, IPC-2581, NC drill files, and pick-and-place centroid files).\u003C/li>\n\u003C/ol>\n\u003Ch2>PCB Layout Rules and Constraints Setup\u003C/h2>\n\u003Cp>Before routing a single trace, the layout engineer must establish electrical, mechanical, and fabrication constraints within the EDA tool's constraint manager:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth align=\"left\">Constraint Category\u003C/th>\n\u003Cth align=\"left\">Critical Engineering Rule\u003C/th>\n\u003Cth align=\"left\">Recommended Specification (Standard Tier)\u003C/th>\n\u003Cth align=\"left\">Advanced / HDI Tier\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Clearance (Trace-to-Trace)\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Minimum conductor spacing to prevent shorts and dielectric breakdown\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.127\\text{ mm}$ (5 mil)\u003C/td>\n\u003Ctd align=\"left\">0.075 mm to 0.100 mm (3 to 4 mil)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Trace Width\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Governed by current capacity (per IPC-2152) and impedance targets\u003C/td>\n\u003Ctd align=\"left\">\u003Ca href=\"/en/blog/pcb-trace-width-calculator/\">Calculated trace width\u003C/a> ($\\ge 0.127\\text{ mm}$)\u003C/td>\n\u003Ctd align=\"left\">0.075 mm (3 mil) microstrip\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Via Annular Ring\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Copper ring surrounding drilled hole per IPC-2221 Class 2\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.125\\text{ mm}$ (5 mil)\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.075\\text{ mm}$ (3 mil) laser microvia\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Board Edge Clearance\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Distance from copper traces and planes to routed board outline\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.50\\text{ mm}$ (20 mil) to prevent exposed copper during V-scoring/routing\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.30\\text{ mm}$ (12 mil)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Solder Mask Dam\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Minimum green oil bridge width between adjacent SMD pads\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.10\\text{ mm}$ (4 mil) to eliminate solder bridging\u003C/td>\n\u003Ctd align=\"left\">0.065 mm to 0.075 mm (2.5 to 3 mil)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Drill-to-Copper Clearance\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Distance from through-hole drill hole wall to unrelated inner layer copper\u003C/td>\n\u003Ctd align=\"left\">$\\ge 0.25\\text{ mm}$ (10 mil)\u003C/td>\n\u003Ctd align=\"left\">0.18 mm to 0.20 mm\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Establishing these constraints upfront ensures that the board passes automated fabrication checks without requiring manual geometry redesigns during CAM tooling.\u003C/p>\n\u003Ch2>Component Placement Best Practices\u003C/h2>\n\u003Cp>Component placement dictates 80% to 90% of routing success. Poor placement cannot be compensated for by clever routing.\u003C/p>\n\u003Ch3>1. Functional Partitioning and Floorplanning\u003C/h3>\n\u003Cp>Divide the board into isolated functional domains:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Power Stage\u003C/strong>: Switching regulators, buck/boost converters, input filter inductors, and bulk capacitors.\u003C/li>\n\u003Cli>\u003Cstrong>Digital Core\u003C/strong>: Microcontrollers, FPGAs, high-speed RAM, flash memory, and peripheral logic.\u003C/li>\n\u003Cli>\u003Cstrong>Sensitive Analog\u003C/strong>: Operational amplifiers, precision references, ADCs, and sensor signal conditioning.\u003C/li>\n\u003Cli>\u003Cstrong>RF / Wireless\u003C/strong>: Transceivers, matching networks, bandpass filters, and printed or ceramic antennas.\u003C/li>\n\u003C/ul>\n\u003Cp>Keep analog and digital circuits physically separated. Never route high-speed digital tracks across analog sections, and maintain clean separation of return current paths.\u003C/p>\n\u003Ch3>2. Strategic Placement Hierarchy\u003C/h3>\n\u003Cp>Follow a strict chronological placement sequence:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Fixed Mechanical Components\u003C/strong>: Connectors, switches, LEDs, heatsinks, and mounting screws defined by the enclosure mechanical design.\u003C/li>\n\u003Cli>\u003Cstrong>Core Processing ICs\u003C/strong>: Microprocessors, DSPs, and high-pin-count \u003Ca href=\"/en/blog/what-is-bga/\">BGA packages\u003C/a>. Place these centrally relative to their associated memory and peripheral interfaces to minimize total bus length.\u003C/li>\n\u003Cli>\u003Cstrong>Power Management ICs\u003C/strong>: Place linear regulators and switching converters close to the board power entrance, with output stages oriented directly toward downstream loads.\u003C/li>\n\u003Cli>\u003Cstrong>Bypass and Decoupling Capacitors\u003C/strong>: Position capacitors as close as physically possible to the target IC supply pins. For fine-pitch packages, place 0402 or 0201 high-frequency decoupling capacitors directly on the opposite side of the board beneath the IC power pins.\u003C/li>\n\u003Cli>\u003Cstrong>Oscillators and Resonators\u003C/strong>: Place crystals immediately adjacent to MCU clock pins. Route no signals beneath the crystal on adjacent layers, and surround the oscillator circuitry with a solid ground guard ring to suppress parasitic coupling.\u003C/li>\n\u003C/ul>\n\u003Ch3>3. Thermal Management in Placement\u003C/h3>\n\u003Cp>High-power discrete components (MOSFETs, power inductors, LED arrays) must be spaced evenly across the board to prevent localized thermal hotspots. Avoid clustering power transistors next to temperature-sensitive analog references, electrolytic capacitors, or crystal resonators. Align power-dissipating components with the chassis airflow direction to maximize forced convection heat transfer.\u003C/p>\n\u003Ch2>Advanced Routing Techniques\u003C/h2>\n\u003Cp>Once component placement is locked, routing translates logical net topology into high-performance physical transmission lines.\u003C/p>\n\u003Ch3>1. Routing Hierarchy\u003C/h3>\n\u003Cp>Execute routing in order of sensitivity and critical timing:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Critical Clocks and Sensitive Analog Nets\u003C/strong>: Route clock lines directly with minimum layer transitions.\u003C/li>\n\u003Cli>\u003Cstrong>High-Speed Differential Pairs\u003C/strong>: USB, PCIe, HDMI, Ethernet, and DDR memory bus strobes.\u003C/li>\n\u003Cli>\u003Cstrong>High-Current Power Traces\u003C/strong>: Use wide copper pours or dedicated internal planes rather than narrow traces.\u003C/li>\n\u003Cli>\u003Cstrong>General-Purpose Low-Speed I/O\u003C/strong>: GPIOs, status indicators, and control signals.\u003C/li>\n\u003C/ol>\n\u003Ch3>2. Angular Bends and Acid Trap Avoidance\u003C/h3>\n\u003Cp>Never use 90° sharp corners on signal traces. Sharp right-angle corners cause localized impedance drops (due to the effective trace width increasing by 41% across the diagonal) and act as "acid traps" during chemical etching, where manufacturing etchants become trapped and over-etch the copper neck. Always route corners using \u003Cstrong>45° mitered bends\u003C/strong> or smooth curved arcs.\u003C/p>\n\u003Ch3>3. High-Speed Differential Pair Guidelines\u003C/h3>\n\u003Cul>\n\u003Cli>\u003Cstrong>Consistent Intra-Pair Spacing ($S$)\u003C/strong>: Keep the distance between the positive and negative traces constant along their entire route.\u003C/li>\n\u003Cli>\u003Cstrong>Strict Length Matching\u003C/strong>: Match trace lengths within each pair to within $\\pm 0.127\\text{ mm}$ ($\\pm 5\\text{ mil}$) to prevent differential skew and common-mode radiation.\u003C/li>\n\u003Cli>\u003Cstrong>Continuous Reference Ground Plane\u003C/strong>: Route differential pairs over an unbroken solid ground reference plane. Never cross splits or slots in underlying power or ground planes. Crossing a plane split forces the high-frequency return current to take a wide loop around the gap, creating a massive loop antenna that destroys signal integrity and fails EMC emission limits.\u003C/li>\n\u003Cli>\u003Cstrong>Phase-Matched Via Transitions\u003C/strong>: When changing layers, place ground stitching vias adjacent to both signal vias to provide an immediate low-impedance return current path between reference planes.\u003C/li>\n\u003C/ul>\n\u003Ch3>4. Crosstalk Mitigation and the 3W Rule\u003C/h3>\n\u003Cp>To prevent electromagnetic coupling between adjacent parallel signal traces, apply the \u003Cstrong>3W Rule\u003C/strong>: the center-to-center distance between two parallel microstrip traces must be at least three times the trace width ($D \\ge 3 \\times W$). For critical high-frequency clocks or sensitive RF lines, expand this spacing to 5W or 10W, or insert grounded coplanar shielding traces.\u003C/p>\n\u003Ch2>PCB Layout Best Practices and Common Pitfalls\u003C/h2>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth align=\"left\">Design Pitfall\u003C/th>\n\u003Cth align=\"left\">Physical Cause\u003C/th>\n\u003Cth align=\"left\">Engineering Consequence\u003C/th>\n\u003Cth align=\"left\">Corrective Layout Action\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Split Ground Plane Return Loop\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">High-frequency trace crosses a split in the underlying reference plane\u003C/td>\n\u003Ctd align=\"left\">Massive return current loop, excessive EMI, severe signal distortion\u003C/td>\n\u003Ctd align=\"left\">Maintain solid, unbroken ground planes beneath all high-speed signals.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Dangling Stubs on High-Speed Nets\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Branching traces left over from test points or schematic routing edits\u003C/td>\n\u003Ctd align=\"left\">Signal reflections at high frequencies causing ringing and false logic triggers\u003C/td>\n\u003Ctd align=\"left\">Remove all stubs; route multi-drop nets strictly as daisy-chain or fly-by topologies.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Decoupling Capacitor Inductance\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Long traces connecting capacitor pads to IC pins or vias\u003C/td>\n\u003Ctd align=\"left\">High parasitic inductance ($L \\approx 1\\text{ nH/mm}$) negating high-frequency noise suppression\u003C/td>\n\u003Ctd align=\"left\">Place vias directly at capacitor pads; connect directly to internal planes with wide traces.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Switching Power Loop di/dt Noise\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Large loop area between buck switch node, diode/MOSFET, and input cap\u003C/td>\n\u003Ctd align=\"left\">Intense radiated magnetic fields coupling into nearby sensitive circuitry\u003C/td>\n\u003Ctd align=\"left\">Minimize the physical loop area formed by the input capacitor, high-side FET, and low-side FET.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd align=\"left\">\u003Cstrong>Thermal Starvation of Vias\u003C/strong>\u003C/td>\n\u003Ctd align=\"left\">Connecting heavy power planes to SMD pads without thermal relief\u003C/td>\n\u003Ctd align=\"left\">Solder heat sinks into plane during assembly, causing cold solder joints\u003C/td>\n\u003Ctd align=\"left\">Use 4-spoke thermal relief patterns on plane connections to SMD pads.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>Application-Specific Layout Requirements\u003C/h2>\n\u003Cp>Layout rules differ significantly across different circuit domains:\u003C/p>\n\u003Ch3>1. High-Power Switching Power Converters\u003C/h3>\n\u003Cp>In buck and boost regulators, current changes instantaneously ($di/dt > 1\\text{ A/ns}$). Minimize the surface area of the \u003Cstrong>Switch Node (SW)\u003C/strong> copper pour to limit capacitive electric-field coupling, while minimizing the perimeter loop of the input capacitor to ground to limit magnetic-field radiation.\u003C/p>\n\u003Ch3>2. High-Frequency RF Circuits\u003C/h3>\n\u003Cp>RF microstrip and grounded coplanar waveguide (GCPW) traces require tight impedance matching (50 $\\Omega \\pm 5%$). Use solid stitching via fences along both sides of RF lines, spaced at intervals of $\\le \\lambda / 10$ of the highest operating frequency. Ensure that the \u003Ca href=\"/en/blog/solder-paste/\">solder paste\u003C/a> and surface finishes (ENIG, immersion silver) are accounted for in RF loss calculations.\u003C/p>\n\u003Ch3>3. Mixed-Signal Layout (ADCs and DACs)\u003C/h3>\n\u003Cp>Do not physically split ground planes into separate analog and digital islands; modern high-performance converters benefit most from a \u003Cstrong>single, unified ground plane\u003C/strong> combined with disciplined physical placement partitioning. Keep all digital return currents physically isolated on the digital side of the board so they never flow beneath precision analog circuitry.\u003C/p>\n\u003Cp>To review design files, verify stackups, or execute automated DFM analysis for your PCB layout, engage our engineering support through our \u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing services\u003C/a> and \u003Ca href=\"/en/products/pcb-assembly/\">turnkey assembly operations\u003C/a>.\u003C/p>\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>What is the difference between PCB placement and routing?\u003C/h3>\n\u003Cp>Component placement is the spatial arrangement of components on the board surface, grouping functional blocks, orienting thermal dissipators, and optimizing bus lengths. Routing is the subsequent process of drawing physical copper traces to electrically connect the placed component pins according to the schematic netlist and impedance rules.\u003C/p>\n\u003Ch3>What are the most important PCB layout rules?\u003C/h3>\n\u003Cp>The most critical layout rules are: maintaining a continuous, unbroken ground reference plane beneath all high-speed signals; keeping decoupling capacitors immediately adjacent to IC power pins; minimizing high-frequency current loop areas (especially in switching power supplies); using 45° mitered corners instead of 90° bends; and enforcing the 3W spacing rule between parallel traces to eliminate crosstalk.\u003C/p>\n\u003Ch3>What causes crosstalk in a PCB layout and how do you prevent it?\u003C/h3>\n\u003Cp>Crosstalk is caused by mutual capacitive and inductive electromagnetic coupling between adjacent parallel traces running close to each other. It is prevented by increasing track separation (following the 3W rule where center-to-center spacing is $\\ge 3\\times$ trace width), keeping traces close to an underlying solid ground plane, and inserting grounded shielding copper between sensitive nets.\u003C/p>\n\u003Ch3>Why should 90-degree corners be avoided in PCB traces?\u003C/h3>\n\u003Cp>Sharp 90-degree corners should be avoided for two reasons: from a manufacturing standpoint, sharp inner angles act as acid traps that retain chemical etching solutions and cause conductor necking or open circuits; from an electrical standpoint, the corner increases local trace capacitance, creating an impedance discontinuity that causes signal reflections on gigabit-speed signals.\u003C/p>\n\u003Ch3>What is the best PCB layout software?\u003C/h3>\n\u003Cp>Industry-standard PCB layout software includes Altium Designer (dominant in commercial enterprise and hardware startups), Cadence Allegro and OrCAD (widely used in enterprise high-speed computing, automotive, and telecom), Siemens Xpedition (used in aerospace and defense), and KiCad (the leading open-source EDA tool for engineers and makers).\u003C/p>\n\u003Cp>Aligning copper clearance parameters with standard \u003Ca href=\"/en/blog/circuit-board/\">pcb board production\u003C/a> constraints minimizes solder bridging and etching undercut.\u003C/p>\n\u003Cp>Engineers should verify layer stackups and impedance profiles on a \u003Ca href=\"/en/services/pcb-prototype/\">prototype circuit board\u003C/a> before freezing gerbers for multi-panel arrays.\u003C/p>\n\u003Cp>Restricting total layer count to balanced even configurations (e.g. 4 or 6 layers) is a fundamental lever for \u003Ca href=\"/en/blog/pcb-cost/\">low cost pcb manufacturing\u003C/a> without sacrificing shielding.\u003C/p>\n\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/pcb-materials-guide/\">PCB Materials Guide: FR4, High-Tg, Rogers, Polyimide, Aluminum and Ceramic\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-trace-width-calculator/\">PCB Trace Width Calculator: IPC-2152 Formula, Current Capacity and Worked Examples\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/what-is-bga/\">What Is a BGA (Ball Grid Array)? Package Types, Solder Balls and PCB Use\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/solder-paste/\">What Is Solder Paste? Composition, Alloys, Storage and How It Is Used in SMT\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing services\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/pcb-assembly/\">turnkey assembly operations\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/circuit-board/\">Circuit Board Manufacturing: Complete PCB Production Process Guide 2025\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[],[15,16,17,18,19,20,21,22,23,24],"pcb layout","pcb layout design","pcb layout rules","pcb component placement","pcb routing techniques","pcb layout guidelines","pcb routing rules","pcb trace routing","pcb layout best practices","pcb layout tutorial","pcb-layout-guide","en",{"blog":28,"breadcrumb":37},{"@context":29,"@type":30,"headline":4,"description":5,"image":8,"url":31,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":32,"articleSection":7,"author":33,"publisher":36},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pcb-layout-guide/","pcb layout, pcb layout design, pcb layout rules, pcb component placement, pcb routing techniques, pcb layout guidelines, pcb routing rules, pcb trace routing, pcb layout best practices, pcb layout tutorial",{"@type":34,"name":35},"Organization","HILPCB",{"@type":34,"name":35},{"@context":29,"@type":38,"itemListElement":39},"BreadcrumbList",[40,45,49],{"@type":41,"position":42,"name":43,"item":44},"ListItem",1,"Home","https://hilpcb.com/",{"@type":41,"position":46,"name":47,"item":48},2,"Blog","https://hilpcb.com/en/blog/",{"@type":41,"position":50,"name":25,"item":31},3,1791623033634]