[{"data":1,"prerenderedAt":64},["ShallowReactive",2],{"blog-pcb-test-coupons-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":28,"slug":33,"sourceLocale":34,"availableLocales":35,"jsonld":40},"PCB Test Coupons: What to Specify and Which Reports to Request","Specify PCB test coupons for controlled impedance (TDR), metallographic microsectioning, and daisy-chain thermal cycling. Learn how to evaluate coupon reports and disposition holds.","2026-10-26","technology","/assets/blogs/pcb-test-coupons/coupon-purpose-map.svg",11,2169,"PT11M","\u003Cp>Writing \u003Cem>"Include standard test coupons"\u003C/em> in a PCB fabrication note leaves the most important quality and procurement variables undefined: which physical structures are placed on the production panel rails, which test procedures are run on them, and what numerical acceptance criteria govern shipment release. Because you cannot saw a customer-shipping board in half to measure inner-layer plating thickness—and you cannot land a high-frequency coaxial TDR probe cleanly on a dense BGA breakout trace loaded with stubs—test coupons serve as \u003Cstrong>purpose-built sacrificial proxies\u003C/strong> manufactured on the same panel as the product boards.\u003C/p>\n\u003Cp>To make coupon data actionable during incoming quality inspection (IQC), each coupon must match the exact layer stack, hole aspect ratio, or conductor geometry of the product board, and every lab report must tie its serial ID back to the specific manufacturing panel and lot. For detailed TDR waveform setup and impedance calculation, see our \u003Ca href=\"/en/blog/impedance-testing/\">PCB impedance testing guide\u003C/a>.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/blogs/pcb-test-coupons/coupon-purpose-map.svg\" alt=\"Manufacturing panel showing TDR impedance, metallographic microsection, and thermal daisy-chain test coupons\">\u003C/p>\n\u003Ch2>1. Matching Coupon Architecture to the Engineering Verification Task\u003C/h2>\n\u003Cp>A single coupon geometry cannot validate electrical impedance, hole-wall metallurgy, and long-term thermal cycling simultaneously. Before panelization freezes, map each project verification requirement to its dedicated coupon structure and governing \u003Ca href=\"https://www.ipc.org/test-methods\">IPC-TM-650 test method\u003C/a>:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Verification Objective\u003C/th>\n\u003Cth>Panel Coupon Structure\u003C/th>\n\u003Cth>Governing Method Basis\u003C/th>\n\u003Cth>What the Coupon Measures\u003C/th>\n\u003Cth>What Passing Does \u003Cstrong>Not\u003C/strong> Prove\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Controlled Impedance (\u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub>\u003C/span> / \u003Cspan class=\"math-inline\">Z\u003Csub>diff\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>Layer-specific single-ended and differential transmission lines with dedicated GND-Signal probe launches\u003C/td>\n\u003Ctd>\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-5-5-7a.pdf\">IPC-TM-650 2.5.5.7A\u003C/a>; \u003Ca href=\"https://www.polarinstruments.com/support/cits/AP8525.pdf\">Polar AP8525\u003C/a>\u003C/td>\n\u003Ctd>Characteristic impedance over a defined uniform line window after etching, lamination, and solder-mask application\u003C/td>\n\u003Ctd>Full-channel insertion loss (\u003Cspan class=\"math-inline\">S\u003Csub>21\u003C/sub>\u003C/span>), laminate \u003Cspan class=\"math-inline\">D\u003Csub>f\u003C/sub>\u003C/span>, or connector/via-transition discontinuities on the product board\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>PTH / Microvia Metallurgy & Laminate Integrity\u003C/strong>\u003C/td>\n\u003Ctd>Metallographic cross-section coupon (or sacrificial product board) containing the smallest drill sizes and via stacks\u003C/td>\n\u003Ctd>\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-1-01f.pdf\">IPC-TM-650 2.1.1F\u003C/a> (preparation) + \u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2.6.8e.pdf\">IPC-TM-650 2.6.8E\u003C/a> (thermal stress)\u003C/td>\n\u003Ctd>Barrel copper thickness, knee wrap, inner-layer foil connection (etchback/smear), resin fill, and post-thermal-shock delamination\u003C/td>\n\u003Ctd>100% netlist continuity across all holes on the shipping boards (requires IPC-9252 electrical test)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Interconnect Thermal-Cycling Endurance\u003C/strong>\u003C/td>\n\u003Ctd>Stitched 4-wire Kelvin daisy-chain coupon cycling through target via spans\u003C/td>\n\u003Ctd>\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-6_2-6-26a.pdf\">IPC-TM-650 2.6.26A\u003C/a> (DC current-induced cycling / IST)\u003C/td>\n\u003Ctd>Resistance drift (\u003Cspan class=\"math-inline\">Δ R\u003C/span>) under repeated thermomechanical Z-axis expansion cycles past laminate \u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span>\u003C/td>\n\u003Ctd>Unconditional field service lifetime in years without an application-specific acceleration model\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Surface Cleanliness / Solderability / Peel\u003C/strong>\u003C/td>\n\u003Ctd>Dedicated comb-pattern (SIR), unpopulated surface-finish pads, or peel-strip specimens\u003C/td>\n\u003Ctd>IPC-TM-650 2.3.25 (ROSE), 2.6.3.7 (SIR), J-STD-003\u003C/td>\n\u003Ctd>Ionic contamination equivalent, insulation resistance under humidity bias, or initial pad wetting\u003C/td>\n\u003Ctd>Post-SMT assembly cleanliness after customer reflow or hand rework\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>\u003Cem>(Downloadable planning matrix: \u003Ca href=\"/assets/blogs/pcb-test-coupons/specimen-selection-and-quote.csv\">specimen-selection-and-quote.csv\u003C/a>.)\u003C/em>\u003C/p>\n\u003Cp>Note that \u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-1-01f.pdf\">IPC-TM-650 2.1.1 Revision F\u003C/a> explicitly permits metallographic microsections to be taken from \u003Cstrong>either a dedicated test coupon or an actual printed board\u003C/strong> containing the features of interest, and notes that multiple section planes may be required when different hole families (such as through-holes, blind laser microvias, and buried core vias) exist in the same stackup.\u003C/p>\n\u003Ch2>2. Three Technical Requirements That Determine Coupon Representativeness\u003C/h2>\n\u003Cp>A coupon sharing the same panel border as your PCB can still produce misleading results if its local geometry or measurement setup diverges from the product board:\u003C/p>\n\u003Ch3>A. Impedance Coupons: Coating State and the TDR Evaluation Window\u003C/h3>\n\u003Cp>When a TDR step generator injects a fast edge into an impedance coupon, the initial part of the waveform includes inductive/capacitive aberrations from the probe tips and launch pads, while the far end reflects off the open termination. As illustrated in \u003Ca href=\"https://www.polarinstruments.com/support/cits/AP8525.pdf\">Polar Instruments Application Note AP8525\u003C/a>, the test program must define a stable \u003Cstrong>evaluation window\u003C/strong> (commonly 20% to 80% of the coupon trace length, or a specified time window in picoseconds) that excludes launch and end effects without selectively cropping out real mid-line impedance dips.\u003C/p>\n\u003Cp>Equally important is \u003Cstrong>surface condition parity\u003C/strong> (\u003Ca href=\"https://www.polarinstruments.com/support/cits/AP8502.html\">Polar AP8502\u003C/a>): if outer-layer controlled-impedance microstrip lines on the product board are covered with liquid photoimageable (LPI) solder mask—which typically lowers single-ended impedance by \u003Cspan class=\"math-inline\">2--3 Ω\u003C/span>—the impedance coupon trace must receive the exact same solder-mask coating.\u003C/p>\n\u003Ch3>B. Microsection Coupons: Smallest Drill Diameter and Plane A–A Accuracy\u003C/h3>\n\u003Cp>Electroplating throwing power is lowest inside the \u003Cstrong>highest-aspect-ratio (smallest diameter, deepest span) holes\u003C/strong>. If your board contains \u003Cspan class=\"math-inline\">0.15 mm\u003C/span> mechanical vias alongside \u003Cspan class=\"math-inline\">0.80 mm\u003C/span> connector holes, a microsection coupon that only sections \u003Cspan class=\"math-inline\">0.50 mm\u003C/span> holes cannot verify barrel copper thickness in the \u003Cspan class=\"math-inline\">0.15 mm\u003C/span> vias. Furthermore, during manual or semi-automatic grinding (\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-1-01f.pdf\">IPC-TM-650 2.1.1F\u003C/a>), the polish plane (\u003Ccode>Plane A–A\u003C/code>) must intersect within \u003Cspan class=\"math-inline\">± 10%\u003C/span> of the true hole center diameter; under-polishing or over-polishing off-center distorts apparent wall thickness and hides inner-layer foil separation.\u003C/p>\n\u003Ch3>C. Daisy-Chain Thermal Cycling: Capturing Post-\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span> Z-Axis Expansion\u003C/h3>\n\u003Cp>In \u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-6_2-6-26a.pdf\">IPC-TM-650 2.6.26A\u003C/a> (DC current-induced thermal cycling / IST), direct current heats internal interconnect chains between ambient temperature and assembly/stress temperatures while a 4-wire Kelvin bridge continuously tracks resistance change (\u003Cspan class=\"math-inline\">Δ R\u003C/span>). Above the laminate glass-transition temperature (\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span>), Z-axis thermal expansion jumps sharply (for example, from ~45 ppm/°C pre-\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span> to >200 ppm/°C post-\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span> in standard high-\u003Cspan class=\"math-inline\">T\u003Csub>g\u003C/sub>\u003C/span> epoxies), pulling vertically on plated via barrels and microvia-to-target interfaces. Section 5.1.2 of the method distinguishes \u003Cstrong>random sampling\u003C/strong>, \u003Cstrong>selective sampling\u003C/strong> (targeting high-risk panel zones), and \u003Cstrong>comparative sampling\u003C/strong> across process lots—making coupon location and copper density critical when comparing two laminate systems.\u003C/p>\n\u003Ch2>3. Worked Report Audit: Separating Identity, Measurement, and Disposition\u003C/h2>\n\u003Cp>When reviewing incoming supplier coupon reports, audit \u003Cstrong>specimen identity and revision\u003C/strong>, \u003Cstrong>measured values against the contracted window\u003C/strong>, and \u003Cstrong>nonconformance disposition\u003C/strong> independently. A green "PASS" stamp on a summary sheet does not override an out-of-spec line item or a mismatched revision.\u003C/p>\n\u003Cp>Consider four coupon records submitted for panel \u003Ccode>P01\u003C/code> of order \u003Ccode>DEMO-100\u003C/code> (contracted to \u003Cstrong>Revision B\u003C/strong>, with project requirements of \u003Cspan class=\"math-inline\">50 Ω ± 10%\u003C/span> single-ended, \u003Cspan class=\"math-inline\">100 Ω ± 5%\u003C/span> differential, and a drawing callout of \u003Cspan class=\"math-inline\">≥ 22 μm\u003C/span> minimum local PTH barrel copper):\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Record ID\u003C/th>\n\u003Cth>Order / Rev\u003C/th>\n\u003Cth>Panel / Coupon ID\u003C/th>\n\u003Cth>Verification Test\u003C/th>\n\u003Cth>Contracted Acceptance Window\u003C/th>\n\u003Cth>Reported Result\u003C/th>\n\u003Cth>Engineering Audit & Disposition\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>R01\u003C/strong>\u003C/td>\n\u003Ctd>DEMO-100 / \u003Cstrong>Rev B\u003C/strong>\u003C/td>\n\u003Ctd>P01 / \u003Ccode>Z-L1-01\u003C/code>\u003C/td>\n\u003Ctd>L1 Single-Ended TDR (IPC-TM-650 2.5.5.7A)\u003C/td>\n\u003Ctd>\u003Cspan class=\"math-inline\">50 Ω ± 10%\u003C/span> (\u003Cspan class=\"math-inline\">45.0--55.0 Ω\u003C/span>)\u003C/td>\n\u003Ctd>\u003Cstrong>52.0 Ω\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>PASS\u003C/strong> — Matches Rev B identity and sits within the \u003Cspan class=\"math-inline\">45.0--55.0 Ω\u003C/span> window\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>R02\u003C/strong>\u003C/td>\n\u003Ctd>DEMO-100 / \u003Cstrong>Rev B\u003C/strong>\u003C/td>\n\u003Ctd>P01 / \u003Ccode>Z-L3-01\u003C/code>\u003C/td>\n\u003Ctd>L3 Differential TDR (IPC-TM-650 2.5.5.7A)\u003C/td>\n\u003Ctd>\u003Cspan class=\"math-inline\">100 Ω ± 5%\u003C/span> (\u003Cspan class=\"math-inline\">95.0--105.0 Ω\u003C/span>)\u003C/td>\n\u003Ctd>\u003Cstrong>106.0 Ω\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>HOLD (Out of Spec)\u003C/strong> — Exceeds \u003Cspan class=\"math-inline\">105.0 Ω\u003C/span> upper limit by \u003Cspan class=\"math-inline\">+1.0 Ω\u003C/span>; cannot be waived by R01 passing\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>R03\u003C/strong>\u003C/td>\n\u003Ctd>DEMO-100 / \u003Cstrong>Rev A\u003C/strong>\u003C/td>\n\u003Ctd>P01 / \u003Ccode>Z-L1-01\u003C/code>\u003C/td>\n\u003Ctd>L1 Single-Ended TDR\u003C/td>\n\u003Ctd>\u003Cspan class=\"math-inline\">50 Ω ± 10%\u003C/span> (\u003Cspan class=\"math-inline\">45.0--55.0 Ω\u003C/span>)\u003C/td>\n\u003Ctd>\u003Cstrong>49.0 Ω\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>HOLD (Revision Mismatch)\u003C/strong> — Value is within band, but test program/coupon references superseded \u003Cstrong>Rev A\u003C/strong> stackup\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>R04\u003C/strong>\u003C/td>\n\u003Ctd>DEMO-100 / \u003Cstrong>Rev B\u003C/strong>\u003C/td>\n\u003Ctd>P01 / \u003Ccode>M-PTH-01\u003C/code>\u003C/td>\n\u003Ctd>PTH Cross-Section (\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-1-01f.pdf\">IPC-TM-650 2.1.1F\u003C/a>)\u003C/td>\n\u003Ctd>Drawing callout: local barrel Cu \u003Cspan class=\"math-inline\">≥ 22 μm\u003C/span>\u003C/td>\n\u003Ctd>\u003Cstrong>21 µm\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>HOLD (Below Drawing Spec)\u003C/strong> — Meets standard Class 2 \u003Cspan class=\"math-inline\">20 μm\u003C/span> average, but falls \u003Cspan class=\"math-inline\">1 μm\u003C/span> below customer drawing callout\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>\u003Cem>(Downloadable report audit dataset: \u003Ca href=\"/assets/blogs/pcb-test-coupons/illustrative-report-results.csv\">illustrative-report-results.csv\u003C/a> and \u003Ca href=\"/assets/blogs/pcb-test-coupons/README.md\">notes\u003C/a>.)\u003C/em>\u003C/p>\n\u003Ch3>How to Investigate and Close Each Hold Without Losing Traceability\u003C/h3>\n\u003Col>\n\u003Cli>\u003Cstrong>Closing \u003Ccode>R02\u003C/code> (106.0 Ω Differential TDR Hold):\u003C/strong> Do not silently re-probe the coupon with a narrower evaluation window just to hunt for a number below \u003Cspan class=\"math-inline\">105.0 Ω\u003C/span>. First verify probe polarity, calibration standard, and whether the measurement included a launch reflection. Next, cross-check the L3 microsection (\u003Ccode>M-PTH-01\u003C/code>) to see if pressed prepreg thickness came out thicker than nominal or if L3 trace width was over-etched. If the physical board truly sits at \u003Cspan class=\"math-inline\">106.0 Ω\u003C/span>, the design/SI authority must decide whether to grant a lot-specific engineering concession (MRB waiver) or reject the affected panel(s), preserving the original \u003Ccode>R02\u003C/code> log alongside the disposition.\u003C/li>\n\u003Cli>\u003Cstrong>Closing \u003Ccode>R03\u003C/code> (Revision A vs. Revision B Mismatch):\u003C/strong> An in-band impedance number (\u003Cspan class=\"math-inline\">49.0 Ω\u003C/span>) is invalid if the operator loaded the Revision A TDR test recipe or if CAM stepped an outdated Revision A coupon onto a Revision B panel. Quarantine the lot until CAM confirms whether the physical panel etched Revision B artwork (requiring only a corrected test-program header and re-test) or Revision A artwork (requiring lot rejection).\u003C/li>\n\u003Cli>\u003Cstrong>Closing \u003Ccode>R04\u003C/code> (21 µm Barrel Copper vs. 22 µm Drawing Spec):\u003C/strong> Verify measurement uncertainty on the optical/SEM microscope, check the other five wall measurement zones in the section, and section a backup coupon from the center and corner of panel \u003Ccode>P01\u003C/code> to establish whether plating thickness was low across the bath load or localized to one rail position.\u003C/li>\n\u003C/ol>\n\u003Ch2>4. Procurement Cost Drivers and Panel Utilization Tradeoffs\u003C/h2>\n\u003Cp>Adding custom coupons and laboratory reports affects quotation scope in four concrete ways that procurement should normalize across competing suppliers:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Panel Border Utilization:\u003C/strong> Standard impedance and microsection coupons fit within routine \u003Cspan class=\"math-inline\">10--20 mm\u003C/span> manufacturing rails. Long differential insertion-loss coupons (such as \u003Cspan class=\"math-inline\">100--150 mm\u003C/span> SET2DIL / VNA structures) or large IST daisy-chain coupons consume active panel area and can reduce the number of shipping boards per panel.\u003C/li>\n\u003Cli>\u003Cstrong>Sampling Frequency (Per-Lot vs. Per-Panel):\u003C/strong> Specifying 100% per-panel TDR testing and per-panel microsectioning provides panel-level isolation if one press opening or plating rack drifts, whereas lot-level sampling (e.g., 1–2 panels per batch) lowers lab labor cost for stable repeat builds.\u003C/li>\n\u003Cli>\u003Cstrong>Conditioning Protocol Before Sectioning:\u003C/strong> Evaluating an as-fabricated microsection is faster than running 3× or 6× solder-float thermal shock (\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2.6.8e.pdf\">IPC-TM-650 2.6.8E\u003C/a> at \u003Cspan class=\"math-inline\">288°C\u003C/span> for \u003Cspan class=\"math-inline\">10 s\u003C/span>) or convection reflow simulation (\u003Ca href=\"https://www.ipc.org/TOC/IPC-9631.pdf\">IPC-9631\u003C/a> / 2.6.27) prior to potting and polishing.\u003C/li>\n\u003Cli>\u003Cstrong>Physical Mount & Coupon Retention:\u003C/strong> Specify whether cured epoxy microsection pucks, remaining unsectioned coupons, and raw \u003Ccode>.csv\u003C/code> / TDR waveform files must ship in the box with the PCBs or remain archived at the factory for a defined retention period.\u003C/li>\n\u003C/ul>\n\u003Ch2>5. RFQ Checklist for PCB Test Coupons and Quality Deliverables\u003C/h2>\n\u003Cp>When submitting a \u003Ca href=\"/en/blog/controlled-impedance-pcb-design-review/\">controlled-impedance design review\u003C/a> or \u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing inquiry\u003C/a>, include these fields in your fabrication drawing and PO notes:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Coupon Types Required:\u003C/strong> Explicitly call out TDR impedance coupons (listing every controlled layer, trace width/space, reference planes, and target \u003Cspan class=\"math-inline\">Ω ± %\u003C/span>), metallographic microsection coupons (covering the smallest PTH, blind/buried vias, and VIPPO structures), and any thermal-cycling or cleanliness specimens.\u003C/li>\n\u003Cli>\u003Cstrong>Serialization & Traceability:\u003C/strong> Require each board and its corresponding panel coupons to share a laser-marked or etched \u003Cstrong>Panel ID\u003C/strong> (\u003Ccode>Panel #01\u003C/code>, \u003Ccode>Panel #02\u003C/code>, etc.) so a failing coupon isolates the exact affected boards rather than placing the entire production lot in blind quarantine.\u003C/li>\n\u003Cli>\u003Cstrong>Test Standards & Conditioning:\u003C/strong> State the governing standard and revision (e.g., IPC-6012 Class 2 or Class 3, IPC-TM-650 2.5.5.7A for TDR, IPC-TM-650 2.6.8E Condition A for thermal stress).\u003C/li>\n\u003Cli>\u003Cstrong>Deliverable Package:\u003C/strong> Specify high-resolution annotated microsection micrographs (with scale bars and measured copper/dielectric dimensions), TDR waveform plots showing the evaluation window, and raw pass/fail data tables.\u003C/li>\n\u003C/ol>\n\u003Cp>HILPCB provides in-house TDR impedance verification (supporting \u003Cstrong>±10% standard and ±5% advanced tolerances\u003C/strong>), sample-based VNA S-parameter testing up to \u003Cstrong>40 GHz\u003C/strong>, metallographic cross-section analysis, thermal-stress testing, and \u003Cstrong>IST interconnect cycling (200–500 cycles)\u003C/strong> across our \u003Ca href=\"/en/products/multilayer-pcb/\">multilayer PCB\u003C/a> and \u003Ca href=\"/en/products/hdi-pcb/\">HDI PCB\u003C/a> lines. Upload your Gerber files and stackup requirements when you \u003Ca href=\"/en/quote/\">request a quote\u003C/a> to lock your coupon layout and inspection deliverables before panelization.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>Does a passing TDR impedance coupon prove my high-speed channel will pass insertion-loss requirements?\u003C/h3>\n\u003Cp>No. A standard TDR coupon (\u003Ca href=\"https://www.ipc.org/sites/default/files/test_methods_docs/2-5-5-7a.pdf\">IPC-TM-650 2.5.5.7A\u003C/a>) verifies characteristic impedance (\u003Cspan class=\"math-inline\">Z\u003Csub>0\u003C/sub>\u003C/span> or \u003Cspan class=\"math-inline\">Z\u003Csub>diff\u003C/sub>\u003C/span>) determined primarily by trace width, dielectric thickness, and real permittivity (\u003Cspan class=\"math-inline\">D\u003Csub>k\u003C/sub>\u003C/span>). It does not measure dielectric loss tangent (\u003Cspan class=\"math-inline\">D\u003Csub>f\u003C/sub>\u003C/span>) or high-frequency copper roughness loss, which require broadband VNA S-parameter (\u003Cspan class=\"math-inline\">S\u003Csub>21\u003C/sub>\u003C/span>) or differential phase/loss test structures.\u003C/p>\n\u003Ch3>Why must panel coupons be serialized to individual manufacturing panels?\u003C/h3>\n\u003Cp>Lamination press pressure, copper electroplating current density, and etching uniformity can vary from panel to panel across a production lot. If coupons and shipping boards are stamped with matching panel numbers (\u003Ccode>P01\u003C/code>, \u003Ccode>P02\u003C/code>, etc.), an out-of-spec TDR or microsection result on \u003Ccode>P02\u003C/code> allows quality engineering to quarantine or disposition \u003Ccode>P02\u003C/code> specifically—and verify whether neighboring panels are affected—rather than losing traceability across the entire shipment.\u003C/p>\n\u003Ch3>Can the fabricator place microsection and impedance coupons on the breakaway panel rails?\u003C/h3>\n\u003Cp>Yes, placing coupons on the manufacturing panel rails (or customer sub-panel rails) is standard practice because those zones experience the same lamination press cycle, drilling setup, plating bath, and etching line as the product boards without consuming finished board area. For large panels or critical Class 3 builds, diagonally opposite rail coupons (e.g., diagonally at two panel corners) are commonly used to capture center-to-edge plating and press-thickness gradients.\u003C/p>\n\u003Ch3>Should solder mask be applied over outer-layer impedance coupon traces?\u003C/h3>\n\u003Cp>The coupon must match the finished product board. If your outer-layer controlled-impedance microstrip traces are covered by solder mask on the PCB, the corresponding coupon traces must also be coated with the same solder mask. Leaving the coupon trace bare air-microstrip while coating the product board will make the coupon read \u003Cspan class=\"math-inline\">2--3 Ω\u003C/span> higher than the actual traces on the shipped PCB.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/impedance-testing/\">Impedance Testing for Signal Integrity in PCB Manufacturing\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pcb-test-coupons/specimen-selection-and-quote.csv\">specimen-selection-and-quote.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pcb-test-coupons/illustrative-report-results.csv\">illustrative-report-results.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pcb-test-coupons/README.md\">notes\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/controlled-impedance-pcb-design-review/\">Controlled Impedance PCB Design Review Before Fabrication Release\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/pcb-manufacturing/\">PCB manufacturing inquiry\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/multilayer-pcb/\">multilayer PCB\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,18,22,25],{"question":15,"answer":16,"answerText":17},"Does a passing TDR impedance coupon prove my high-speed channel will pass insertion-loss requirements?","No. A standard TDR coupon ([IPC-TM-650 2.5.5.7A](https://www.ipc.org/sites/default/files/test_methods_docs/2-5-5-7a.pdf)) verifies characteristic impedance ($Z_0$ or $Z_{\\text{diff}}$) determined primarily by trace width, dielectric thickness, and real permittivity ($D_k$). It does not measure dielectric loss tangent ($D_f$) or high-frequency copper roughness loss, which require broadband VNA S-parameter ($S_{21}$) or differential phase/loss test structures.","No. A standard TDR coupon (IPC-TM-650 2.5.5.7A) verifies characteristic impedance ($Z_0$ or $Z_{\\text{diff}}$) determined primarily by trace width, dielectric thickness, and real permittivity ($D_k$). It does not measure dielectric loss tangent ($D_f$) or high-frequency copper roughness loss, which require broadband VNA S-parameter ($S_{21}$) or differential phase/loss test structures.",{"question":19,"answer":20,"answerText":21},"Why must panel coupons be serialized to individual manufacturing panels?","Lamination press pressure, copper electroplating current density, and etching uniformity can vary from panel to panel across a production lot. If coupons and shipping boards are stamped with matching panel numbers (`P01`, `P02`, etc.), an out-of-spec TDR or microsection result on `P02` allows quality engineering to quarantine or disposition `P02` specifically—and verify whether neighboring panels are affected—rather than losing traceability across the entire shipment.","Lamination press pressure, copper electroplating current density, and etching uniformity can vary from panel to panel across a production lot. If coupons and shipping boards are stamped with matching panel numbers (P01, P02, etc.), an out-of-spec TDR or microsection result on P02 allows quality engineering to quarantine or disposition P02 specifically—and verify whether neighboring panels are affected—rather than losing traceability across the entire shipment.",{"question":23,"answer":24,"answerText":24},"Can the fabricator place microsection and impedance coupons on the breakaway panel rails?","Yes, placing coupons on the manufacturing panel rails (or customer sub-panel rails) is standard practice because those zones experience the same lamination press cycle, drilling setup, plating bath, and etching line as the product boards without consuming finished board area. For large panels or critical Class 3 builds, diagonally opposite rail coupons (e.g., diagonally at two panel corners) are commonly used to capture center-to-edge plating and press-thickness gradients.",{"question":26,"answer":27,"answerText":27},"Should solder mask be applied over outer-layer impedance coupon traces?","The coupon must match the finished product board. If your outer-layer controlled-impedance microstrip traces are covered by solder mask on the PCB, the corresponding coupon traces must also be coated with the same solder mask. Leaving the coupon trace bare air-microstrip while coating the product board will make the coupon read $2\\text{--}3\\ \\Omega$ higher than the actual traces on the shipped PCB.",[29,30,31,32],"pcb test coupons","TDR impedance coupon","PCB microsection","IPC-TM-650","pcb-test-coupons","en",[34,36,37,38,39],"de","cn","fr","ru",{"blog":41,"breadcrumb":50},{"@context":42,"@type":43,"headline":4,"description":5,"image":8,"url":44,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":45,"articleSection":7,"author":46,"publisher":49},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pcb-test-coupons/","pcb test coupons, TDR impedance coupon, PCB microsection, IPC-TM-650",{"@type":47,"name":48},"Organization","HILPCB",{"@type":47,"name":48},{"@context":42,"@type":51,"itemListElement":52},"BreadcrumbList",[53,58,62],{"@type":54,"position":55,"name":56,"item":57},"ListItem",1,"Home","https://hilpcb.com/",{"@type":54,"position":59,"name":60,"item":61},2,"Blog","https://hilpcb.com/en/blog/",{"@type":54,"position":63,"name":33,"item":44},3,1793496913771]