[{"data":1,"prerenderedAt":64},["ShallowReactive",2],{"blog-pcb-via-inductance-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":26,"slug":32,"sourceLocale":33,"availableLocales":34,"jsonld":40},"PCB Via Inductance: Length, Diameter and Return Paths","Calculate a single via's geometry-based inductance, compare shorter barrels, and understand why return paths and rise time matter for real PCB transitions.","2026-11-08","technology","/assets/img/blogs/2026/11/pcb-via-inductance-cover.svg",6,1044,"PT6M","\u003Cp>A via contributes inductance even when its DC resistance is small. For a first geometry comparison, reducing barrel length usually changes the estimate more strongly than a modest diameter increase. The return path remains essential: a single-via calculation cannot determine the inductance of the complete signal or power loop.\u003C/p>\n\u003Cp>Use the \u003Ca href=\"/en/tools/pcb-via-inductance-calculator/\">PCB via inductance calculator\u003C/a> to compare dimensions and inspect ideal inductive reactance versus frequency. Keep the geometry estimate separate from the insertion loss or bandwidth of a complete transition.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/img/blogs/2026/11/pcb-via-inductance.svg\" alt=\"A signal barrel of length h and diameter d with a nearby return via; the simple formula describes only the signal barrel\">\u003C/p>\n\u003Ch2>What does the via inductance formula calculate?\u003C/h2>\n\u003Cp>The tool implements the single-via approximation in \u003Ca href=\"https://www.ti.com/lit/an/slla284g/slla284g.pdf\">Texas Instruments SLLA284G, Equation 2, printed page 16\u003C/a>:\u003C/p>\n\u003Cp>\u003Cstrong>L [nH] = 0.2 × h [mm] × {ln[4h/d] + 1}\u003C/strong>\u003C/p>\n\u003Cp>Here h is the modeled via length and d is the via diameter. Use the same length unit inside the logarithm and the natural logarithm, ln. The 0.2 coefficient above is for h in millimetres and L in nanohenries. The diameter d is not the pad or antipad diameter.\u003C/p>\n\u003Cp>The calculator screens geometry to h ≥ d and dimensions from 0.01 to 100 mm. That is an application screen to avoid unsuitable shapes, not a published guarantee of accuracy throughout the range. A short, wide interconnect needs an appropriate field model rather than forcing it through this equation.\u003C/p>\n\u003Cp>This approximation does not include a nearby return conductor, plane coupling, mutual inductance between vias, pad capacitance or a stub resonance. Selecting h should describe the segment you are evaluating; editing h does not automatically model the rest of a partially used through via.\u003C/p>\n\u003Ch2>Worked example: shorten the via or enlarge its diameter?\u003C/h2>\n\u003Cp>Set h = 1.60 mm, d = 0.30 mm and frequency = 1000 MHz. Change one dimension at a time:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Geometry\u003C/th>\n\u003Cth>Length h\u003C/th>\n\u003Cth>Diameter d\u003C/th>\n\u003Cth>Estimated L\u003C/th>\n\u003Cth>Change in L\u003C/th>\n\u003Cth>Ideal XL at 1 GHz\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Baseline\u003C/td>\n\u003Ctd>1.60 mm\u003C/td>\n\u003Ctd>0.30 mm\u003C/td>\n\u003Ctd>1.29929 nH\u003C/td>\n\u003Ctd>—\u003C/td>\n\u003Ctd>8.16366 Ω\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>25% shorter\u003C/td>\n\u003Ctd>1.20 mm\u003C/td>\n\u003Ctd>0.30 mm\u003C/td>\n\u003Ctd>0.905421 nH\u003C/td>\n\u003Ctd>−30.31%\u003C/td>\n\u003Ctd>5.68893 Ω\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>50% shorter\u003C/td>\n\u003Ctd>0.80 mm\u003C/td>\n\u003Ctd>0.30 mm\u003C/td>\n\u003Ctd>0.538740 nH\u003C/td>\n\u003Ctd>−58.54%\u003C/td>\n\u003Ctd>3.38500 Ω\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>25% wider diameter\u003C/td>\n\u003Ctd>1.60 mm\u003C/td>\n\u003Ctd>0.375 mm\u003C/td>\n\u003Ctd>1.22788 nH\u003C/td>\n\u003Ctd>−5.50%\u003C/td>\n\u003Ctd>7.71500 Ω\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The difference follows from the equation: length multiplies the entire expression and also appears inside the logarithm. Diameter appears only inside the logarithm. These results support a geometry comparison for this example; they do not imply that every design should use a thinner board or a larger drill.\u003C/p>\n\u003Cp>A wider hole also changes annular-ring requirements, routing space and fabrication constraints. A shorter barrel can require another layer assignment or a different via construction. Compare those consequences with the \u003Ca href=\"/en/tools/pcb-impedance-calculator/\">impedance and stackup workbench\u003C/a> before changing the design.\u003C/p>\n\u003Ch2>Why does frequency change reactance but not this inductance?\u003C/h2>\n\u003Cp>The geometry-only approximation returns the same L at every evaluation frequency. Ideal inductive reactance is:\u003C/p>\n\u003Cp>\u003Cstrong>XL [Ω] = 2π × f [MHz] × L [nH] × 0.001\u003C/strong>\u003C/p>\n\u003Cp>For the baseline 1.29929 nH, XL is about 0.816366 Ω at 100 MHz and 8.16366 Ω at 1 GHz. At DC its ideal reactance is zero, but the real barrel still has copper resistance. The \u003Ca href=\"/en/tools/pcb-via-current-calculator/\">via current calculator\u003C/a> handles that separate DC resistance estimate.\u003C/p>\n\u003Cp>An 8.16 Ω reactance is not an 8.16 Ω resistance and does not mean the transition dissipates power like an 8.16 Ω resistor. It also does not directly specify reflection or insertion loss without the surrounding circuit and return structure.\u003C/p>\n\u003Ch2>Should you enter clock frequency or rise time?\u003C/h2>\n\u003Cp>Fast edges contain frequency content above the clock repetition rate. A 25 MHz clock with a 1 ns edge should not be assessed only at 25 MHz.\u003C/p>\n\u003Cp>The tool's rise-time mode uses \u003Cstrong>feval [MHz] = 350 / tr [ns]\u003C/strong>. A 1 ns edge therefore selects 350 MHz and gives about 2.85728 Ω for the baseline geometry. This is the 0.35/tr bandwidth estimate for a single-pole 10–90% rise-time convention. It is not the highest harmonic of every waveform or a complete channel specification.\u003C/p>\n\u003Cp>Record whether the rise time is measured, simulated or specified, along with its measurement definition and loading. Use the actual driver and receiver models when the transition can affect a timing or signal-integrity margin.\u003C/p>\n\u003Ch2>What does a nearby return via change?\u003C/h2>\n\u003Cp>A signal changing reference planes needs a suitable return-current path between those references. Moving the return path far away can enlarge the current loop even if the signal barrel dimensions stay unchanged. A nearby ground return via can help when it connects the relevant ground references, but its effect depends on spacing and the complete stackup.\u003C/p>\n\u003Cp>The single-via formula does not change when you move that return via because return geometry is absent from its inputs. Do not divide its L by the number of parallel vias to claim a loop-inductance result: mutual coupling and current distribution matter.\u003C/p>\n\u003Cp>For a critical transition, model the signal via, pads, antipads, connected traces, reference planes, return conductors and unused stub together. Correlate the model with the measurement appropriate to the project. \u003Ca href=\"https://www.ti.com/lit/an/slla414/slla414.pdf\">TI's High-Speed Layout Guidelines\u003C/a> provide further layout context.\u003C/p>\n\u003Ch2>FAQ\u003C/h2>\n\u003C!-- faq:start -->\n\n\u003Ch3>Does doubling via diameter halve its inductance?\u003C/h3>\n\u003Cp>No. Diameter enters a logarithm in this approximation. For the stated baseline, a 25% increase reduces the estimate by about 5.50%.\u003C/p>\n\u003Ch3>Can I use the result as the complete loop inductance?\u003C/h3>\n\u003Cp>No. Return geometry and mutual coupling are absent. Use a loop or field model that includes the actual current path.\u003C/p>\n\u003Ch3>Does a lower inductance prove better high-speed performance?\u003C/h3>\n\u003Cp>It can be useful, but capacitance, impedance discontinuities, stubs, loss and return continuity also matter. A lower isolated L does not prove a better complete channel.\u003C/p>\n\u003Ch3>Can I combine the inductance and capacitance calculators to find a via resonance?\u003C/h3>\n\u003Cp>They provide separate geometry approximations. Substituting their outputs into an ideal LC equation does not establish the resonance or usable bandwidth of a distributed multilayer transition.\u003C/p>\n\u003C!-- faq:end -->\n\n\u003Cp>\u003Ca href=\"/en/tools/pcb-via-inductance-calculator/\">Explore the length and diameter comparison\u003C/a> and read the companion \u003Ca href=\"/en/blog/pcb-via-capacitance/\">via capacitance guide\u003C/a> before reviewing the complete transition.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/tools/pcb-via-inductance-calculator/\">PCB via inductance calculator\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/tools/pcb-impedance-calculator/\">impedance and stackup workbench\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/tools/pcb-via-current-calculator/\">via current calculator\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-via-capacitance/\">PCB Via Capacitance: Pad, Antipad and Board Thickness\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23],{"question":15,"answer":16,"answerText":16},"Does doubling via diameter halve its inductance?","No. Diameter enters a logarithm in this approximation. For the stated baseline, a 25% increase reduces the estimate by about 5.50%.",{"question":18,"answer":19,"answerText":19},"Can I use the result as the complete loop inductance?","No. Return geometry and mutual coupling are absent. Use a loop or field model that includes the actual current path.",{"question":21,"answer":22,"answerText":22},"Does a lower inductance prove better high-speed performance?","It can be useful, but capacitance, impedance discontinuities, stubs, loss and return continuity also matter. A lower isolated L does not prove a better complete channel.",{"question":24,"answer":25,"answerText":25},"Can I combine the inductance and capacitance calculators to find a via resonance?","They provide separate geometry approximations. Substituting their outputs into an ideal LC equation does not establish the resonance or usable bandwidth of a distributed multilayer transition.",[27,28,29,30,31],"PCB via inductance","via length","return path","signal integrity","rise time","pcb-via-inductance","en",[33,35,36,37,38,39],"de","it","cn","fr","ru",{"blog":41,"breadcrumb":50},{"@context":42,"@type":43,"headline":4,"description":5,"image":8,"url":44,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":45,"articleSection":7,"author":46,"publisher":49},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pcb-via-inductance/","PCB via inductance, via length, return path, signal integrity, rise time",{"@type":47,"name":48},"Organization","HILPCB",{"@type":47,"name":48},{"@context":42,"@type":51,"itemListElement":52},"BreadcrumbList",[53,58,62],{"@type":54,"position":55,"name":56,"item":57},"ListItem",1,"Home","https://hilpcb.com/",{"@type":54,"position":59,"name":60,"item":61},2,"Blog","https://hilpcb.com/en/blog/",{"@type":54,"position":63,"name":32,"item":44},3,1794155573914]