[{"data":1,"prerenderedAt":64},["ShallowReactive",2],{"blog-pcba-test-false-failures-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":29,"slug":33,"sourceLocale":34,"availableLocales":35,"jsonld":40},"PCBA Test False Failures: How to Separate Fixture and Board Faults","Investigate PCBA test failures with controlled fixture comparisons and independent verification, while preserving first-failure and disposition records.","2026-10-25","testing",null,13,2535,"PT13M","\u003Cp>An unexpected ICT or FCT failure should first trigger \u003Cstrong>quarantine and investigation\u003C/strong>, not a “false failure” label. A passing retest, reseating the board, or changing fixtures can narrow the investigation, but none proves that the original result was wrong. Classify a result as a false reject only after independent verification against the applicable requirements and an authorized, signed adjudication.\u003C/p>\n\u003Cp>The practical approach is to preserve the first-failure evidence, compare controlled board and fixture combinations, check the deployed test configuration, and independently measure the failed characteristic. Keep intermittent board defects and measurement uncertainty in the investigation until the evidence resolves them.\u003C/p>\n\u003Cp>For background on test access, \u003Ca href=\"/en/blog/pcb-test-points/\">PCB test points\u003C/a> covers probe geometry and false opens in more detail. This article focuses on the diagnostic process across the fixture, board, program, measurement system and environment. The broader methods are also explained in \u003Ca href=\"/en/blog/ict-testing/\">ICT testing\u003C/a> and \u003Ca href=\"/en/blog/pcb-functional-testing/\">PCB functional testing\u003C/a>.\u003C/p>\n\u003Ch2>What a first failure does—and does not—mean\u003C/h2>\n\u003Cp>A first failure establishes that a particular test system, under its conditions at that moment, reported a result outside its acceptance criteria or could not complete the measurement. It does not by itself establish why.\u003C/p>\n\u003Cp>Possible explanations include:\u003C/p>\n\u003Cul>\n\u003Cli>A real board defect, including an intermittent connection or component.\u003C/li>\n\u003Cli>Poor contact between a probe and its intended test point.\u003C/li>\n\u003Cli>A fixture, cable, relay or interface fault.\u003C/li>\n\u003Cli>An incorrect test program, product variant, BOM revision or firmware configuration.\u003C/li>\n\u003Cli>A measurement affected by circuit loading, parallel paths or an incorrect assumption.\u003C/li>\n\u003Cli>A power, calibration or environmental condition that affects the result.\u003C/li>\n\u003C/ul>\n\u003Cp>More than one cause can coexist. For example, a board with a marginal pad or solder joint may be sensitive to normal fixture contact variation. A change in outcome after reseating therefore identifies an interaction worth investigating; it does not automatically clear the board.\u003C/p>\n\u003Cp>Separate the \u003Cstrong>test result\u003C/strong> from the \u003Cstrong>product disposition\u003C/strong>. A production system may flag or reject a unit when it fails, while the subsequent technical review determines whether the unit actually conformed, had a defect, or remains unresolved.\u003C/p>\n\u003Ch2>Preserve the first-failure evidence\u003C/h2>\n\u003Cp>Before troubleshooting changes the conditions, record the original result and place the unit in the agreed hold status. Preserve the test record rather than replacing the first result with a later pass.\u003C/p>\n\u003Cp>Useful first-failure fields include:\u003C/p>\n\u003Cul>\n\u003Cli>Board serial number, assembly part number and revision, and manufacturing lot where applicable.\u003C/li>\n\u003Cli>Test type, station, fixture identification and test-program revision actually used.\u003C/li>\n\u003Cli>Product variant, applicable BOM revision and DUT firmware revision where relevant.\u003C/li>\n\u003Cli>Date and time, failed test step, net or function, and the instrument or channel involved.\u003C/li>\n\u003Cli>Raw numeric reading, units, applied limits and any instrument or tester error message.\u003C/li>\n\u003Cli>Power state, test sequence, operator actions and relevant environmental conditions.\u003C/li>\n\u003Cli>Subsequent retests, reseating, configuration changes and their results, linked to the original event.\u003C/li>\n\u003C/ul>\n\u003Cp>Raw values matter. A resistance just outside a limit, an overload indication and a missing-contact error may all appear as “fail,” but they call for different checks. Preserve timestamps and the sequence of actions so that a later pass can be interpreted in context.\u003C/p>\n\u003Cp>Follow the site’s electrical safety, stored-energy and ESD procedures. \u003Cstrong>Power off and verify a safe state before checking or handling fixture contacts\u003C/strong>, cables or boards, unless an approved procedure specifically requires an energized measurement. Do not defeat interlocks or probe accessible live circuits without an authorized method and suitable equipment.\u003C/p>\n\u003Ch2>Compare boards and fixtures without changing everything at once\u003C/h2>\n\u003Cp>A controlled comparison is often the fastest way to identify where to investigate next. Use the failing board, called \u003Cstrong>board A\u003C/strong>, and a controlled reference board, called \u003Cstrong>board B\u003C/strong>. If compatible, test each with the suspect fixture and an independently checked comparison fixture.\u003C/p>\n\u003Cp>Keep the station, program, product variant, relevant settings and test sequence constant where practicable. If any factor must change, record it. A fixture swap that also changes the station or program is a useful observation, but it cannot isolate the fixture.\u003C/p>\n\u003Cp>A schematic example:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Combination\u003C/th>\n\u003Cth>Illustrative result\u003C/th>\n\u003Cth>What it contributes\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Board A, fixture X\u003C/td>\n\u003Ctd>Fail\u003C/td>\n\u003Ctd>Reproduces the reported combination.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Board A, fixture Y\u003C/td>\n\u003Ctd>Pass\u003C/td>\n\u003Ctd>Suggests sensitivity to a changed fixture or its interface; does not prove board A is sound.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Board B, fixture X\u003C/td>\n\u003Ctd>Pass\u003C/td>\n\u003Ctd>Shows fixture X can pass board B under this setup; does not prove every contact is sound.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Board B, fixture Y\u003C/td>\n\u003Ctd>Pass\u003C/td>\n\u003Ctd>Provides a comparison result, not blanket validation of either board or fixture.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>This pattern points to an interaction involving board A and fixture X. The next step is to check the specific failed contact or measurement independently, including the physical condition of board A. Repeated cycles may help reveal intermittency, but only within approved limits: repeated powered tests, insertions or thermal cycles can themselves affect a marginal assembly.\u003C/p>\n\u003Ch3>Control the reference board\u003C/h3>\n\u003Cp>A “golden board” is useful only if its identity, revision, condition and relevant characteristics are controlled. Establish what was independently verified, by whom, using which method and when. Check that its configuration matches the test being run, and maintain a process for detecting damage or changes.\u003C/p>\n\u003Cp>Do not assume that a reference board is correct because it passed previously. It can develop a fault, differ from the current product revision, or fail to represent a marginal condition. Likewise, validate comparison-fixture settings and interfaces independently rather than treating a previous pass as proof.\u003C/p>\n\u003Ch2>Use failure patterns to choose the next check\u003C/h2>\n\u003Cp>The table below guides investigation; it does not replace adjudication against the applicable requirements.\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Observation\u003C/th>\n\u003Cth>Candidate causes\u003C/th>\n\u003Cth>Next independent check\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>One net fails on several boards with one fixture\u003C/td>\n\u003Ctd>Probe contact, alignment, wiring, relay or program issue\u003C/td>\n\u003Ctd>Inspect and verify the affected path; compare with a controlled fixture and appropriate board revisions.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>One board fails the same characteristic on compatible fixtures\u003C/td>\n\u003Ctd>DUT defect, board-specific contact condition or incorrect test assumption\u003C/td>\n\u003Ctd>Inspect the feature and independently measure the characteristic using an approved method.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Failure moves when a cable or fixture is changed\u003C/td>\n\u003Ctd>Interface, fixture or cable issue; possibly a disturbance of an intermittent DUT\u003C/td>\n\u003Ctd>Identify exactly what changed and verify the implicated path without assuming the DUT is clear.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Many unrelated tests fail together\u003C/td>\n\u003Ctd>Power, common return, interlock, configuration or shared measurement path\u003C/td>\n\u003Ctd>Check supply behavior, connections and deployed configuration against approved settings.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>A result alternates around a limit\u003C/td>\n\u003Ctd>Measurement variation, contact instability, drift or marginal product behavior\u003C/td>\n\u003Ctd>Review raw readings, repeatability, uncertainty and the applicable decision rule.\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>FCT fails but ICT passes\u003C/td>\n\u003Ctd>Functional behavior not covered by ICT, firmware, setup or an intermittent defect\u003C/td>\n\u003Ctd>Reproduce the functional condition and independently verify the failed requirement.\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>Look for clustering by fixture, station, shift, lot, board revision, test step and time. A common pattern can prioritize checks, but correlation is not root cause. A board lot may coincide with a fixture change, for example, so the records must distinguish those events.\u003C/p>\n\u003Ch2>Investigate the fixture and contact path\u003C/h2>\n\u003Cp>With power safely removed, examine the relevant probe pins, alignment and mechanical interfaces under the approved procedure. Check for damage, contamination, wear or an obstruction that could prevent consistent contact. Inspect the board’s corresponding test point as well: an issue visible on the DUT may not be a fixture fault.\u003C/p>\n\u003Cp>The IPC-hosted paper \u003Cstrong>In-Circuit Test Prove Contact\u003C/strong> documents that flux residue and surface conditions affected contact in its experimental context. That supports checking those conditions, not assuming residue is the cause of every contact failure.\u003C/p>\n\u003Cp>Also trace the measurement path beyond the probe:\u003C/p>\n\u003Cul>\n\u003Cli>Verify the appropriate cable and connector seating and identification.\u003C/li>\n\u003Cli>Check the relevant relay and channel using an approved verification method.\u003C/li>\n\u003Cli>Compare the actual fixture configuration with the released fixture and test documentation.\u003C/li>\n\u003Cli>Inspect for signs that a fixture change affects more than one measurement path.\u003C/li>\n\u003Cli>Document any cleaning, adjustment or repair before retesting, including the method and responsible person.\u003C/li>\n\u003C/ul>\n\u003Cp>After maintenance, verify the affected function and record the result before returning the fixture to production use. A subsequent pass alone does not establish which intervention mattered if several changes were made at once.\u003C/p>\n\u003Ch2>Check the program, measurement and DUT separately\u003C/h2>\n\u003Ch3>Confirm the deployed configuration\u003C/h3>\n\u003Cp>Compare what the tester actually executed with the released test package—not just what the station screen was expected to load. Review the assembly revision, BOM or variant, test-program revision, test limits, fixture mapping and any approved engineering changes.\u003C/p>\n\u003Cp>For FCT, include the DUT firmware and configuration, as well as the tester software and test sequence. A mismatch can create an apparent defect or conceal a real one. Do not change a program, disable a test or widen a limit merely to obtain a pass. Any change needs technical validation, documented approval and a defined effect on units already tested.\u003C/p>\n\u003Ch3>Validate the measurement method\u003C/h3>\n\u003Cp>An ICT reading is made in the context of a populated circuit. Parallel paths, component behavior and measurement loading can make a simple comparison with an isolated component value misleading. Confirm that the test method and expected value account for the actual circuit and product revision.\u003C/p>\n\u003Cp>Use an independent method appropriate to the characteristic and approved product requirements. Define the measurement points, instrument, settings, setup and any permissible isolation before measuring. Isolation or removal can change or damage the DUT, so it requires authorization and a controlled procedure.\u003C/p>\n\u003Cp>Check calibration status where applicable, but do not equate a current calibration label with proof that the complete probe-to-board measurement is valid. Fixture wiring, contact, setup and the method can still affect the result.\u003C/p>\n\u003Cp>Near a limit, assess measurement uncertainty and the \u003Cstrong>decision rule\u003C/strong> specified for the acceptance decision. The Tektronix \u003Cstrong>Decision Rule Guide\u003C/strong> discusses uncertainty and pass/fail decisions in a calibration context. It is useful background, but its calibration-specific settings are not universal PCBA test limits. If the applicable rule and evidence cannot support a conformance decision, retain the unit as unresolved until the responsible parties agree on a valid disposition.\u003C/p>\n\u003Ch3>Keep intermittent DUT defects in scope\u003C/h3>\n\u003Cp>A board that passes after movement, cooling, warming or reseating may still have a marginal solder joint, connector, component or internal connection. Compare the behavior with the applicable product requirements and investigate the specific feature rather than relying on repeated passes alone.\u003C/p>\n\u003Cp>Relevant defect mechanisms are discussed in \u003Ca href=\"/en/blog/electronic-component-failure-modes/\">electronic component failure modes\u003C/a>. Visual examination can add evidence, as described in \u003Ca href=\"/en/blog/pcb-inspection/\">PCB inspection\u003C/a>, but visual acceptance or a functional pass is not blanket proof of long-term reliability.\u003C/p>\n\u003Ch2>Adjudicate the result, not just the retest\u003C/h2>\n\u003Cp>Before assigning a cause, identify the applicable drawing, specification, test plan, acceptance limits and approved decision rule. Independent verification should address both questions:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Did the DUT meet the applicable requirement?\u003C/strong>\u003C/li>\n\u003Cli>\u003Cstrong>What evidence explains the original failure indication?\u003C/strong>\u003C/li>\n\u003C/ol>\n\u003Cp>A valid outcome may be:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>False reject attributable to the test system:\u003C/strong> Independent evidence establishes DUT conformance under the applicable criteria, and the investigation supports the identified test-system cause.\u003C/li>\n\u003Cli>\u003Cstrong>Confirmed DUT defect:\u003C/strong> Independent evidence establishes nonconformance, even if a later test happens to pass.\u003C/li>\n\u003Cli>\u003Cstrong>Unresolved:\u003C/strong> Evidence is insufficient to decide conformance, cause or both.\u003C/li>\n\u003C/ul>\n\u003Cp>Have the designated authorized reviewer sign the disposition and record the evidence, scope and any remaining limitations. Independence means the adjudication is not simply acceptance of the original tester’s result or the operator’s retest; the project should define who is qualified and authorized to make that decision.\u003C/p>\n\u003Cp>A finding that the failed characteristic conforms is not automatically proof that every other characteristic, or the assembly’s future reliability, has been established. Release remains subject to the complete applicable product and test requirements.\u003C/p>\n\u003Ch2>Illustrative failure accounting\u003C/h2>\n\u003Cp>Suppose \u003Cstrong>200 unique units\u003C/strong> each receive a first test attempt. \u003Cstrong>20 fail\u003C/strong> on that first attempt and are reviewed:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Adjudicated outcome\u003C/th>\n\u003Cth align=\"right\">Units\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>Independently established fixture-related conforming DUTs\u003C/td>\n\u003Ctd align=\"right\">12\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Confirmed DUT defects\u003C/td>\n\u003Ctd align=\"right\">3\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>Unresolved\u003C/td>\n\u003Ctd align=\"right\">5\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Total first failures reviewed\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>20\u003C/strong>\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>The arithmetic is:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>12 / 200 = 6%\u003C/strong> of all units tested were flagged as fixture-related after adjudication.\u003C/li>\n\u003Cli>\u003Cstrong>12 / 20 = 60%\u003C/strong> of the first-fail set were independently established as fixture-related conforming DUTs.\u003C/li>\n\u003C/ul>\n\u003Cp>These are hypothetical figures, not a factory result. Neither percentage is a false-reject rate among all conforming units: the total number of conforming units is unknown in this example. The five unresolved units are not preclassified as conforming or defective. The counts also assume one first attempt per unique unit and that all 20 first failures are included in the review.\u003C/p>\n\u003Ch2>Define responsibilities before release or RFQ\u003C/h2>\n\u003Cp>A useful \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a> RFQ should define testing and disposition responsibilities rather than assuming that assembly, fixture ownership and final product acceptance sit with the same party. Include the following as applicable:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Product definition:\u003C/strong> assembly part number and revision, applicable BOM and variant, approved changes, firmware identification, and product acceptance documents.\u003C/li>\n\u003Cli>\u003Cstrong>Test scope:\u003C/strong> ICT and FCT steps, coverage expectations, limits, decision rules, required records and permitted retest conditions.\u003C/li>\n\u003Cli>\u003Cstrong>Fixture ownership:\u003C/strong> who supplies, verifies, maintains, repairs and releases each fixture; compatibility and identification requirements; and handling of reference boards.\u003C/li>\n\u003Cli>\u003Cstrong>Safety:\u003C/strong> power conditions, interlocks, ESD controls and who approves procedures involving energized measurements.\u003C/li>\n\u003Cli>\u003Cstrong>Configuration control:\u003C/strong> ownership of test programs, settings and firmware; revision approval; deployment checks; and change records.\u003C/li>\n\u003Cli>\u003Cstrong>Failure handling:\u003C/strong> quarantine location or status, escalation contacts, independent verification method, disposition authority and treatment of unresolved units.\u003C/li>\n\u003Cli>\u003Cstrong>Traceability:\u003C/strong> serial or lot identifiers, first-failure raw data and timestamps, retest history, fixture and station IDs, and signed adjudication records.\u003C/li>\n\u003Cli>\u003Cstrong>Release criteria:\u003C/strong> evidence required to return a fixture to use and to release or reject affected units, including the treatment of units tested before a corrective change.\u003C/li>\n\u003C/ul>\n\u003Cp>For a specific project, provide the available files and open questions through the \u003Ca href=\"/en/quote/\">quote request\u003C/a>, or \u003Ca href=\"/en/contact/\">contact HILPCB\u003C/a> to discuss the intended scope. Test execution, fixture work, records and deliverables should be agreed for the project rather than presumed.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\u003C!-- faq:start -->\n\u003Ch2>FAQ\u003C/h2>\n\u003Ch3>Is a passing retest proof of a false failure?\u003C/h3>\n\u003Cp>No. It is evidence of changed behavior. Independent verification and authorized adjudication are needed to distinguish a false reject from an intermittent defect or unresolved result.\u003C/p>\n\u003Ch3>Can a reference board prove a fixture is good?\u003C/h3>\n\u003Cp>No. It helps compare conditions, but it tests only the characteristics and setup involved. Its identity, revision and relevant characteristics must be independently controlled.\u003C/p>\n\u003Ch3>What should be checked first after an unexpected ICT failure?\u003C/h3>\n\u003Cp>Quarantine the unit and preserve the first result, raw value, limits and configuration. Then investigate the failed path using safe, controlled comparisons.\u003C/p>\n\u003Ch3>Can test limits be widened to reduce false failures?\u003C/h3>\n\u003Cp>Not without technical validation and the required approval. Wider limits can hide real nonconformance, and their effect on previously tested units must be addressed.\u003C/p>\n\u003Ch3>Does a functional pass clear a board that failed ICT?\u003C/h3>\n\u003Cp>Not automatically. FCT may not exercise or measure the ICT characteristic. Verify the failed requirement independently and apply the agreed disposition process.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/pcb-test-points/\">PCB Test Point Design: Clearance Rules, Probe Pitch, and ICT vs Flying Probe Economics\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/ict-testing/\">In-Circuit Testing (ICT) for PCBA: Coverage and Fixture Design\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-functional-testing/\">PCB Functional Testing: Coverage, Fixtures, and Production Release\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/electronic-component-failure-modes/\">Electronic Component Failure Modes: Types, Causes and Diagnosis\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/pcb-inspection/\">PCB Inspection Services: AOI, X-Ray, and Quality Control Solutions\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote/\">quote request\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,17,20,23,26],{"question":15,"answer":16,"answerText":16},"Is a passing retest proof of a false failure?","No. It is evidence of changed behavior. Independent verification and authorized adjudication are needed to distinguish a false reject from an intermittent defect or unresolved result.",{"question":18,"answer":19,"answerText":19},"Can a reference board prove a fixture is good?","No. It helps compare conditions, but it tests only the characteristics and setup involved. Its identity, revision and relevant characteristics must be independently controlled.",{"question":21,"answer":22,"answerText":22},"What should be checked first after an unexpected ICT failure?","Quarantine the unit and preserve the first result, raw value, limits and configuration. Then investigate the failed path using safe, controlled comparisons.",{"question":24,"answer":25,"answerText":25},"Can test limits be widened to reduce false failures?","Not without technical validation and the required approval. Wider limits can hide real nonconformance, and their effect on previously tested units must be addressed.",{"question":27,"answer":28,"answerText":28},"Does a functional pass clear a board that failed ICT?","Not automatically. FCT may not exercise or measure the ICT characteristic. Verify the failed requirement independently and apply the agreed disposition process.",[30,31,32],"PCBA false failures","ICT test fixture","functional test","pcba-test-false-failures","en",[34,36,37,38,39],"de","cn","fr","ru",{"blog":41,"breadcrumb":50},{"@context":42,"@type":43,"headline":4,"description":5,"url":44,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":45,"articleSection":7,"author":46,"publisher":49},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pcba-test-false-failures/","PCBA false failures, ICT test fixture, functional test",{"@type":47,"name":48},"Organization","HILPCB",{"@type":47,"name":48},{"@context":42,"@type":51,"itemListElement":52},"BreadcrumbList",[53,58,62],{"@type":54,"position":55,"name":56,"item":57},"ListItem",1,"Home","https://hilpcb.com/",{"@type":54,"position":59,"name":60,"item":61},2,"Blog","https://hilpcb.com/en/blog/",{"@type":54,"position":63,"name":33,"item":44},3,1794062104935]