[{"data":1,"prerenderedAt":66},["ShallowReactive",2],{"blog-pick-and-place-file-checklist-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":30,"slug":35,"sourceLocale":36,"availableLocales":37,"jsonld":42},"Pick-and-Place Files: CPL Fields, Rotation and BOM Matching Checks","Validate PCB pick-and-place (CPL / centroid) files before SMT assembly: verify origin, body-center vs Pin-1 coordinates, zero-degree rotation, bottom-side mirroring, and BOM DNP rules.","2026-10-29","technology","/assets/blogs/pick-and-place-file-checklist/assembly-drawing.svg",11,2143,"PT11M","\u003Cp>Exporting a pick-and-place file—also called a \u003Cstrong>Component Placement List (CPL)\u003C/strong>, \u003Cstrong>centroid file\u003C/strong>, or \u003Cstrong>XYR / \u003Ccode>.pos\u003C/code> file\u003C/strong>—from your EDA tool without reconciling it against the active BOM variant and assembly drawing is one of the most common causes of NPI assembly holds and reversed polarized parts. A CSV file that imports cleanly into SMT programming software can still shift an entire connector off its pads (if the library origin sat on Pin 1 instead of the package body center), mount diodes and ICs rotated \u003Cspan class=\"math-inline\">180°\u003C/span>, or populate components marked \u003Ccode>DNP\u003C/code> (Do Not Populate).\u003C/p>\n\u003Cp>While component sourcing and alternate part approvals belong in your \u003Ca href=\"/en/blog/what-is-a-bom/\">PCBA Bill of Materials (BOM)\u003C/a>, the CPL file governs \u003Cstrong>physical machine coordinates, side assignment, and nozzle rotation\u003C/strong>. Verifying the CPL before release requires locking a seven-point coordinate contract and running both set-level BOM reconciliation and visual overlay checks.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/blogs/pick-and-place-file-checklist/assembly-drawing.svg\" alt=\"Top-view PCBA placement verification drawing showing origin (0,0), populated R1/R2, polarized diode D1 cathode orientation, and excluded C3 DNP\">\u003C/p>\n\u003Ch2>1. The Seven-Point Coordinate & Orientation Contract\u003C/h2>\n\u003Cp>An SMT pick-and-place machine does not interpret schematic symbols; it drives a vacuum nozzle to a numeric \u003Cspan class=\"math-inline\">(X, Y)\u003C/span> offset from the board's fiducial datum and rotates the head by \u003Cspan class=\"math-inline\">θ\u003C/span> degrees relative to the component's carrier-tape pocket orientation. Before exporting placement files (for example, via \u003Ccode>File → Fabrication Outputs → Component Placement (.pos, .gbr)\u003C/code> in \u003Ca href=\"https://docs.kicad.org/9.0/en/pcbnew/pcbnew.html#_component_placement_files\">KiCad 9.0\u003C/a> or \u003Ccode>Generates Pick and Place Files\u003C/code> in Altium Designer), verify these seven parameters:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>CPL Parameter\u003C/th>\n\u003Cth>What the Export Must Define\u003C/th>\n\u003Cth>Common Engineering Failure Mode\u003C/th>\n\u003Cth>Pre-Release Verification Check\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>1. Reference Origin \u003Cspan class=\"math-inline\">(0,0)\u003C/span>\u003C/strong>\u003C/td>\n\u003Ctd>Consistent datum (typically lower-left board outline corner or dedicated \u003Ccode>Drill/Place File Origin\u003C/code>) shared with Gerber/drill files\u003C/td>\n\u003Ctd>Exporting CPL from absolute page origin while Gerbers use auxiliary drill origin shifts every component off the board\u003C/td>\n\u003Ctd>Overlay CPL centroids directly onto Top/Bottom Gerber paste layers and verify fiducial coordinates (\u003Ccode>FID1\u003C/code>–\u003Ccode>FID3\u003C/code>)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>2. Units & Precision\u003C/strong>\u003C/td>\n\u003Ctd>Explicit \u003Ccode>mm\u003C/code> (recommended, minimum 3–4 decimal places) or \u003Ccode>mil\u003C/code>/\u003Ccode>inch\u003C/code> header\u003C/td>\n\u003Ctd>Unlabeled units or integer rounding shifts \u003Cspan class=\"math-inline\">0.35--0.40 mm\u003C/span> pitch BGAs and 0201 passives off-center\u003C/td>\n\u003Ctd>Confirm maximum \u003Cspan class=\"math-inline\">(X, Y)\u003C/span> values match physical board outline dimensions\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>3. Centroid Reference Point\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Geometric center of the component body\u003C/strong> (pick surface center of gravity), \u003Cem>not\u003C/em> Pin 1\u003C/td>\n\u003Ctd>Custom footprints for connectors, shields, or DPAK/SOT parts left with library origin on Pin 1 cause nozzle pick misses or pad offset\u003C/td>\n\u003Ctd>Visually inspect asymmetric connectors, inductors, and multi-pin headers on the paste-layer centroid overlay\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>4. Board Side (\u003Ccode>Top\u003C/code> / \u003Ccode>Bottom\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>Unambiguous side flag (\u003Ccode>Top\u003C/code>/\u003Ccode>Bottom\u003C/code> or \u003Ccode>T\u003C/code>/\u003Ccode>B\u003C/code>) or separate side files\u003C/td>\n\u003Ctd>Through-hole or bottom-mounted decouplers accidentally tagged as \u003Ccode>Top\u003C/code>\u003C/td>\n\u003Ctd>Reconcile top/bottom component counts against top/bottom solder-paste layer apertures\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>5. Bottom-Side X Convention\u003C/strong>\u003C/td>\n\u003Ctd>State whether bottom-side X coordinates are exported \u003Cstrong>viewed from top (through-board)\u003C/strong> or \u003Cstrong>horizontally mirrored (\u003Ccode>Negate bottom X\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>Engineer manually negates bottom X in Excel after CAD already mirrored them, flipping the entire bottom side\u003C/td>\n\u003Ctd>Check one asymmetric off-center bottom component against the bottom solder-paste Gerber view\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>6. Rotation (\u003Cspan class=\"math-inline\">θ\u003C/span> in Degrees)\u003C/strong>\u003C/td>\n\u003Ctd>Counterclockwise angle (\u003Cspan class=\"math-inline\">0°--360°\u003C/span>) from library zero-orientation to placed orientation\u003C/td>\n\u003Ctd>Library footprint built at \u003Cspan class=\"math-inline\">90°\u003C/span> or \u003Cspan class=\"math-inline\">180°\u003C/span> relative to IPC-7351 / EIA-481 tape-pocket standard rotates polarized parts\u003C/td>\n\u003Ctd>Cross-check Pin 1 / cathode bars on the \u003Cstrong>Assembly Drawing\u003C/strong> against actual component footprints\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>7. Population Scope & \u003Ccode>DNP\u003C/code>\u003C/strong>\u003C/td>\n\u003Ctd>Explicit agreement on whether \u003Ccode>DNP\u003C/code>/\u003Ccode>DNI\u003C/code> footprints, fiducials, and test points are omitted from the CPL or flagged in a status column\u003C/td>\n\u003Ctd>CAD exports unpopulated footprints into the CPL because \u003Ccode>Exclude from position files\u003C/code> or \u003Ccode>DNP\u003C/code> filter was left unchecked\u003C/td>\n\u003Ctd>Run set reconciliation between flattened BOM \u003Ccode>Fit\u003C/code> designators and CPL designators\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>2. Worked Reconciliation Exercise: Catching Three Classic CPL Errors\u003C/h2>\n\u003Cp>To see how automated set checks combine with visual polarity verification, download our self-contained reconciliation package for board \u003Ccode>TRAIN-C / Variant A\u003C/code> (\u003Cspan class=\"math-inline\">30.0 × 13.0 mm\u003C/span>, top-side SMT only, origin at bottom-left, \u003Ccode>DNP\u003C/code> parts excluded from the CPL, and diode \u003Ccode>D1\u003C/code> defined with its \u003Cstrong>cathode bar on the LEFT at \u003Cspan class=\"math-inline\">0°\u003C/span>\u003C/strong>):\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Downloadable Exercise Files:\u003C/strong> \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/bom.csv\">bom.csv\u003C/a>, \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/cpl-bad.csv\">cpl-bad.csv\u003C/a>, \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/cpl-good.csv\">cpl-good.csv\u003C/a>, \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/assembly-drawing.svg\">assembly-drawing.svg\u003C/a>, \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/verify.py\">verify.py\u003C/a>, and \u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/README.md\">notes\u003C/a>.\u003C/li>\n\u003C/ul>\n\u003Ch3>Step 1: Compare the BOM Against the Incoming CPL (\u003Ccode>cpl-bad.csv\u003C/code>)\u003C/h3>\n\u003Cp>In \u003Ccode>bom.csv\u003C/code>, three SMT parts are marked \u003Ccode>Fit\u003C/code> (\u003Ccode>R1\u003C/code>, \u003Ccode>R2\u003C/code>, \u003Ccode>D1\u003C/code>) and one capacitor is marked \u003Ccode>DNP\u003C/code> (\u003Ccode>C3\u003C/code>). However, inspecting the incoming \u003Ccode>cpl-bad.csv\u003C/code> alongside \u003Ccode>assembly-drawing.svg\u003C/code> reveals three distinct errors that would cause an assembly build failure if left uncorrected:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Discrepancy Found in \u003Ccode>cpl-bad.csv\u003C/code>\u003C/th>\n\u003Cth>Error Category\u003C/th>\n\u003Cth>Why It Happens in CAD Workflows\u003C/th>\n\u003Cth>Required Fix in \u003Ccode>cpl-good.csv\u003C/code>\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>\u003Ccode>R2\u003C/code> is completely missing\u003C/strong> (\u003Ccode>R1\u003C/code>, \u003Ccode>D1\u003C/code>, \u003Ccode>C3\u003C/code> present)\u003C/td>\n\u003Ctd>\u003Cstrong>Missing Populated Component (\u003Ccode>missing:R2\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>Footprint accidentally had \u003Cem>"Exclude from position files"\u003C/em> or \u003Cem>"Virtual/Mechanical"\u003C/em> checked in library properties\u003C/td>\n\u003Ctd>Uncheck exclusion flag in CAD and restore \u003Ccode>R2\u003C/code> at \u003Ccode>(14, 8), Top, 0°\u003C/code>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>\u003Ccode>C3\u003C/code> is present\u003C/strong> at \u003Ccode>(22, 8), Top, 0°\u003C/code>\u003C/td>\n\u003Ctd>\u003Cstrong>Unintended DNP Inclusion (\u003Ccode>unexpected:C3\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>Designer marked \u003Ccode>C3\u003C/code> as \u003Ccode>DNP\u003C/code> in a custom schematic text field instead of the native CAD \u003Ccode>DNP\u003C/code> attribute, or forgot to enable \u003Cem>"Exclude DNP footprints"\u003C/em> during CPL export\u003C/td>\n\u003Ctd>Enable native DNP exclusion filter and remove \u003Ccode>C3\u003C/code> from the active placement set\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>\u003Ccode>D1\u003C/code> lists \u003Ccode>Rotation_deg = 180\u003C/code>\u003C/strong> at \u003Ccode>(18, 8)\u003C/code>\u003C/td>\n\u003Ctd>\u003Cstrong>Reversed Polarity (\u003Ccode>orientation:D1\u003C/code>)\u003C/strong>\u003C/td>\n\u003Ctd>Footprint cathode bar was drawn on the right at \u003Cspan class=\"math-inline\">0°\u003C/span> in the symbol library, contradicting the assembly drawing's \u003Cspan class=\"math-inline\">0° = Cathode LEFT\u003C/span> contract\u003C/td>\n\u003Ctd>Align rotation to \u003Ccode>0°\u003C/code> (\u003Ccode>cpl-good.csv\u003C/code>) and verify physical cathode bar placement against the silkscreen/assembly drawing\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch3>Step 2: Run the Verification Script and Understand Its Scope\u003C/h3>\n\u003Cp>Running \u003Ccode>python verify.py\u003C/code> in the asset directory compares both CPL files against the expected population set (\u003Ccode>{R1, R2, D1}\u003C/code>), checks for duplicate designator rows, and validates \u003Ccode>D1\u003C/code>'s rotation contract:\u003C/p>\n\u003Cpre>\u003Ccode class=\"language-json\">{"file": "cpl-bad.csv", "errors": ["missing:R2", "unexpected:C3", "orientation:D1"], "count": 3}\n{"file": "cpl-good.csv", "errors": [], "count": 0}\n\u003C/code>\u003C/pre>\n\u003Cp>Notice the engineering boundary between \u003Cstrong>set reconciliation\u003C/strong> and \u003Cstrong>geometric verification\u003C/strong>:\u003C/p>\n\u003Cul>\n\u003Cli>A script comparing BOM and CPL spreadsheets will instantly catch \u003Cstrong>missing designators (\u003Ccode>R2\u003C/code>)\u003C/strong>, \u003Cstrong>unexpected DNP designators (\u003Ccode>C3\u003C/code>)\u003C/strong>, and \u003Cstrong>duplicate rows\u003C/strong> ( remember to expand grouped BOM rows like \u003Ccode>R1, R2, R5\u003C/code> into individual designators first, rather than comparing raw spreadsheet row counts).\u003C/li>\n\u003Cli>However, a spreadsheet script \u003Cstrong>cannot know that \u003Ccode>180°\u003C/code> is backwards for \u003Ccode>D1\u003C/code>\u003C/strong> unless a human or CAM optical system first establishes the physical orientation rule from the \u003Cstrong>Assembly Drawing, Gerber copper/paste layers, and component datasheet\u003C/strong>.\u003C/li>\n\u003C/ul>\n\u003Ch2>3. Why \u003Ccode>(X, Y)\u003C/code> Coordinates Alone Never Establish Orientation\u003C/h2>\n\u003Cp>Even when a component's \u003Cspan class=\"math-inline\">(X, Y)\u003C/span> centroid sits dead-center between its two copper pads, a \u003Cspan class=\"math-inline\">90°\u003C/span> or \u003Cspan class=\"math-inline\">180°\u003C/span> rotation error is invisible until you compare three independent references:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>The Component Manufacturer's Datasheet & EIA-481 Carrier Tape Standard:\u003C/strong> Defines how the physical part sits inside the tape pocket relative to the sprocket holes (pick angle \u003Cspan class=\"math-inline\">0°\u003C/span>).\u003C/li>\n\u003Cli>\u003Cstrong>The CAD Footprint Library Zero-Orientation (\u003Cspan class=\"math-inline\">0°\u003C/span>):\u003C/strong> Under IPC-7351, zero-degree orientation can follow Level A (Pin 1 at upper-left for ICs, cathode left for diodes) or Level B (Pin 1 at lower-left); third-party libraries (SnapEDA, Ultra Librarian, SamacSys, or legacy in-house footprints) often mix both conventions on the same board.\u003C/li>\n\u003Cli>\u003Cstrong>The Assembly Drawing Polarity Markers:\u003C/strong> Clear, unambiguous visual callouts showing \u003Cstrong>Pin 1 dots\u003C/strong>, \u003Cstrong>diode cathode bars (\u003Ccode>|◀\u003C/code>)\u003C/strong>, \u003Cstrong>polarized capacitor \u003Ccode>+\u003C/code> signs\u003C/strong>, and \u003Cstrong>connector keying notches\u003C/strong> directly on the component body outline—not hidden underneath the part where post-placement AOI cannot see them.\u003C/li>\n\u003C/ol>\n\u003Cp>\u003Cstrong>Rule of Thumb for Spreadsheet Edits:\u003C/strong> Never globally add \u003Cspan class=\"math-inline\">+90°\u003C/span> or \u003Cspan class=\"math-inline\">+180°\u003C/span> to a column of rotation angles in Excel without knowing how the assembler's SMT programming software (such as Valor, Unicam, Fuji Flexa, or Yamaha YSUP) maps your CAD library's \u003Cspan class=\"math-inline\">0°\u003C/span> to the feeder tape orientation. Instead, highlight polarized and asymmetric families—\u003Cstrong>diodes, LEDs, tantalum/electrolytic capacitors, BGA/QFN/QFP ICs,SOT-23/SOT-89 packages, and directional sensors/microphones\u003C/strong>—on the assembly drawing and require a visual First Article Inspection (FAI) overlay sign-off.\u003C/p>\n\u003Ch2>4. Diagnosing Systematic CPL Import Anomalies\u003C/h2>\n\u003Cp>When the assembler imports your CPL overlay onto your Gerber solder-paste layers during CAM preflight, the visual error pattern immediately points to the root cause:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Visual Overlay Anomaly in CAM\u003C/th>\n\u003Cth>Root Cause in Export / Import\u003C/th>\n\u003Cth>Correct Fix\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Every component on the board is shifted by the exact same \u003Cspan class=\"math-inline\">(Δ X, Δ Y)\u003C/span> vector\u003C/strong>\u003C/td>\n\u003Ctd>Mismatch between CAD CPL export origin and Gerber/drill export origin\u003C/td>\n\u003Ctd>Re-export CPL and Gerbers using the exact same \u003Ccode>Drill/Place File Origin\u003C/code> (or align origins to lower-left board outline corner + \u003Ccode>FID1\u003C/code>)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Component positions expand or shrink radially from \u003Cspan class=\"math-inline\">(0,0)\u003C/span> by \u003Cspan class=\"math-inline\">25.4×\u003C/span> or \u003Cspan class=\"math-inline\">0.03937×\u003C/span>\u003C/strong>\u003C/td>\n\u003Ctd>Units mismatch (\u003Ccode>mil\u003C/code> vs. \u003Ccode>mm\u003C/code>) or scaling factor applied during import\u003C/td>\n\u003Ctd>Explicitly include unit headers (\u003Ccode>mm\u003C/code>) and re-import at \u003Cspan class=\"math-inline\">1:1\u003C/span> scale\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Top side aligns perfectly, but all Bottom-side components appear mirrored left-to-right\u003C/strong>\u003C/td>\n\u003Ctd>Conflict between CAD \u003Ccode>Negate bottom X\u003C/code> export setting and CAM bottom-view mirror transform\u003C/td>\n\u003Ctd>Confirm whether the CAM system expects unmirrored (top-through-board) or X-mirrored bottom coordinates; toggle once in CAD or CAM, never both\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Centroids sit on pads for passives, but connectors/inductors sit shifted onto Pin 1\u003C/strong>\u003C/td>\n\u003Ctd>Library footprint reference point was placed on Pin 1 instead of geometric body center\u003C/td>\n\u003Ctd>Move footprint pick-origin to package body center (or have CAM snap pick centroids to pad-group bounding-box centers)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>One entire IC package family (e.g., all SOIC-8s) appears rotated \u003Cspan class=\"math-inline\">90°\u003C/span>\u003C/strong>\u003C/td>\n\u003Ctd>Library footprint was drawn vertically at \u003Cspan class=\"math-inline\">0°\u003C/span> while SMT feeder library expects horizontal \u003Cspan class=\"math-inline\">0°\u003C/span>\u003C/td>\n\u003Ctd>Align package rotation offset in the SMT machine library against the Pin 1 dot on the assembly drawing\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>5. Submitting a Synchronized PCBA Release Package\u003C/h2>\n\u003Cp>To avoid NPI engineering queries and prevent component polarity or variant errors, bundle the following synchronized files in your \u003Ca href=\"/en/products/pcb-assembly/\">PCB assembly\u003C/a> or \u003Ca href=\"/en/products/turnkey-assembly/\">turnkey assembly\u003C/a> RFQ (and cross-check sourcing details with our \u003Ca href=\"/en/blog/bom-error-checking-component-procurement/\">BOM error-checking guide\u003C/a>):\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Centroid / Pick-and-Place File (\u003Ccode>.csv\u003C/code> or \u003Ccode>.pos\u003C/code>) or Intelligent \u003Ccode>ODB++\u003C/code> / \u003Ccode>IPC-2581\u003C/code> Archive:\u003C/strong> Containing \u003Ccode>Designator\u003C/code>, \u003Ccode>Mid X (mm)\u003C/code>, \u003Ccode>Mid Y (mm)\u003C/code>, \u003Ccode>Layer/Side (Top/Bottom)\u003C/code>, \u003Ccode>Rotation (deg)\u003C/code>, \u003Ccode>Package/Footprint\u003C/code>, and \u003Ccode>Comment/Value\u003C/code>.\u003C/li>\n\u003Cli>\u003Cstrong>Synchronized BOM with Explicit Variant & \u003Ccode>DNP\u003C/code> Column:\u003C/strong> Ensuring every SMT component marked \u003Ccode>Fit\u003C/code> in the BOM appears exactly once in the CPL, and every \u003Ccode>DNP\u003C/code> component is clearly flagged.\u003C/li>\n\u003Cli>\u003Cstrong>Color PDF Assembly Drawings (Top & Bottom Views):\u003C/strong> Showing reference designators, component outlines, Pin 1 dots, diode cathode bars, and the \u003Cspan class=\"math-inline\">(0,0)\u003C/span> coordinate origin.\u003C/li>\n\u003Cli>\u003Cstrong>Gerber Solder Paste & Copper Layers (\u003Ccode>GTP\u003C/code>/\u003Ccode>GBP\u003C/code>, \u003Ccode>GTL\u003C/code>/\u003Ccode>GBL\u003C/code>):\u003C/strong> Allowing automated CAM centroid-to-paste-pad alignment before stencil cutting and SMT line programming.\u003C/li>\n\u003C/ol>\n\u003Cp>HILPCB's \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a> and \u003Ca href=\"/en/products/pcb-assembly/\">PCB assembly\u003C/a> engineering team runs an automated \u003Cstrong>BOM-to-CPL-to-Gerber centroid overlay check\u003C/strong> on every incoming order—verifying package body centers, Pin 1 / cathode polarity against component datasheets, and DNP exclusions before a single part is mounted, followed by 3D AOI and First Article Inspection (FAI). Upload your Gerber, BOM, and CPL files when you \u003Ca href=\"/en/quote/\">request a quote\u003C/a> to get a rapid DFM/DFA review within 2 hours.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>Why does my CPL have fewer rows than my BOM's total component quantity?\u003C/h3>\n\u003Cp>First, check whether your BOM groups multiple reference designators into a single line item (e.g., \u003Ccode>Qty 4: C1, C2, C3, C4\u003C/code> is 1 BOM row but 4 CPL rows). Second, expand the BOM into individual designators and subtract intentionally excluded items: \u003Ccode>DNP\u003C/code> (Do Not Populate) parts, mechanical hardware (screws, standoffs, heatsinks), bare-board features (fiducials, test points, mounting holes), or manually soldered wire harnesses that are not placed by the automated SMT pick-and-place machine.\u003C/p>\n\u003Ch3>Should I include DNP (Do Not Populate) components in the pick-and-place file?\u003C/h3>\n\u003Cp>Either convention works \u003Cstrong>if it is consistent and explicit\u003C/strong>, though omitting \u003Ccode>DNP\u003C/code> components from the machine placement file (or exporting a dedicated \u003Ccode>Fitted / DNP\u003C/code> status column that matches the BOM 100%) is safest. The worst error is marking a part \u003Ccode>DNP\u003C/code> in a free-text BOM note while leaving it as a normal populated row in the CPL with no \u003Ccode>DNP\u003C/code> flag.\u003C/p>\n\u003Ch3>What is the difference between a footprint's Pin 1 origin and its pick-and-place centroid?\u003C/h3>\n\u003Cp>In CAD library creation, engineers sometimes place the \u003Cspan class=\"math-inline\">(0,0)\u003C/span> coordinate origin on \u003Cstrong>Pin 1\u003C/strong> to make pad layout math easier. However, an SMT pick-and-place vacuum nozzle must pick the component at its \u003Cstrong>geometric body center (center of gravity)\u003C/strong> so the part does not tilt or drop during high-speed travel. Modern EDA tools (like KiCad and Altium) calculate the center of the courtyard/pads or use a dedicated \u003Ccode>Component Center\u003C/code> attribute for CPL export—always verify this on asymmetric connectors and inductors.\u003C/p>\n\u003Ch3>Does Gerber X3 or ODB++ eliminate the need for a separate CSV pick-and-place file?\u003C/h3>\n\u003Cp>Both \u003Cstrong>ODB++\u003C/strong>, \u003Cstrong>IPC-2581\u003C/strong>, and \u003Cstrong>Gerber X3\u003C/strong> embed component centroid, outline, Pin 1, and BOM attribute metadata directly inside the fabrication/assembly dataset, which dramatically reduces origin and mirroring mismatches. Even when using ODB++ or IPC-2581, however, you should still provide a controlled BOM (with approved MPNs and \u003Ccode>DNP\u003C/code> variant flags) and a visual PDF assembly drawing to confirm diode/IC polarity during First Article Inspection.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/what-is-a-bom/\">What Is a BOM in Electronics Manufacturing? PCBA BOM Format, Sample Table, and Sourcing Rules\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/bom.csv\">bom.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/cpl-bad.csv\">cpl-bad.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/cpl-good.csv\">cpl-good.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/assembly-drawing.svg\">assembly-drawing.svg\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/verify.py\">verify.py\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pick-and-place-file-checklist/README.md\">notes\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,18,22,26],{"question":15,"answer":16,"answerText":17},"Why does my CPL have fewer rows than my BOM's total component quantity?","First, check whether your BOM groups multiple reference designators into a single line item (e.g., `Qty 4: C1, C2, C3, C4` is 1 BOM row but 4 CPL rows). Second, expand the BOM into individual designators and subtract intentionally excluded items: `DNP` (Do Not Populate) parts, mechanical hardware (screws, standoffs, heatsinks), bare-board features (fiducials, test points, mounting holes), or manually soldered wire harnesses that are not placed by the automated SMT pick-and-place machine.","First, check whether your BOM groups multiple reference designators into a single line item (e.g., Qty 4: C1, C2, C3, C4 is 1 BOM row but 4 CPL rows). Second, expand the BOM into individual designators and subtract intentionally excluded items: DNP (Do Not Populate) parts, mechanical hardware (screws, standoffs, heatsinks), bare-board features (fiducials, test points, mounting holes), or manually soldered wire harnesses that are not placed by the automated SMT pick-and-place machine.",{"question":19,"answer":20,"answerText":21},"Should I include DNP (Do Not Populate) components in the pick-and-place file?","Either convention works **if it is consistent and explicit**, though omitting `DNP` components from the machine placement file (or exporting a dedicated `Fitted / DNP` status column that matches the BOM 100%) is safest. The worst error is marking a part `DNP` in a free-text BOM note while leaving it as a normal populated row in the CPL with no `DNP` flag.","Either convention works if it is consistent and explicit, though omitting DNP components from the machine placement file (or exporting a dedicated Fitted / DNP status column that matches the BOM 100%) is safest. The worst error is marking a part DNP in a free-text BOM note while leaving it as a normal populated row in the CPL with no DNP flag.",{"question":23,"answer":24,"answerText":25},"What is the difference between a footprint's Pin 1 origin and its pick-and-place centroid?","In CAD library creation, engineers sometimes place the $(0,0)$ coordinate origin on **Pin 1** to make pad layout math easier. However, an SMT pick-and-place vacuum nozzle must pick the component at its **geometric body center (center of gravity)** so the part does not tilt or drop during high-speed travel. Modern EDA tools (like KiCad and Altium) calculate the center of the courtyard/pads or use a dedicated `Component Center` attribute for CPL export—always verify this on asymmetric connectors and inductors.","In CAD library creation, engineers sometimes place the $(0,0)$ coordinate origin on Pin 1 to make pad layout math easier. However, an SMT pick-and-place vacuum nozzle must pick the component at its geometric body center (center of gravity) so the part does not tilt or drop during high-speed travel. Modern EDA tools (like KiCad and Altium) calculate the center of the courtyard/pads or use a dedicated Component Center attribute for CPL export—always verify this on asymmetric connectors and inductors.",{"question":27,"answer":28,"answerText":29},"Does Gerber X3 or ODB++ eliminate the need for a separate CSV pick-and-place file?","Both **ODB++**, **IPC-2581**, and **Gerber X3** embed component centroid, outline, Pin 1, and BOM attribute metadata directly inside the fabrication/assembly dataset, which dramatically reduces origin and mirroring mismatches. Even when using ODB++ or IPC-2581, however, you should still provide a controlled BOM (with approved MPNs and `DNP` variant flags) and a visual PDF assembly drawing to confirm diode/IC polarity during First Article Inspection.","Both ODB++, IPC-2581, and Gerber X3 embed component centroid, outline, Pin 1, and BOM attribute metadata directly inside the fabrication/assembly dataset, which dramatically reduces origin and mirroring mismatches. Even when using ODB++ or IPC-2581, however, you should still provide a controlled BOM (with approved MPNs and DNP variant flags) and a visual PDF assembly drawing to confirm diode/IC polarity during First Article Inspection.",[31,32,33,34],"pick and place file","CPL file","centroid file","SMT component placement","pick-and-place-file-checklist","en",[36,38,39,40,41],"de","cn","fr","ru",{"blog":43,"breadcrumb":52},{"@context":44,"@type":45,"headline":4,"description":5,"image":8,"url":46,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":47,"articleSection":7,"author":48,"publisher":51},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/pick-and-place-file-checklist/","pick and place file, CPL file, centroid file, SMT component placement",{"@type":49,"name":50},"Organization","HILPCB",{"@type":49,"name":50},{"@context":44,"@type":53,"itemListElement":54},"BreadcrumbList",[55,60,64],{"@type":56,"position":57,"name":58,"item":59},"ListItem",1,"Home","https://hilpcb.com/",{"@type":56,"position":61,"name":62,"item":63},2,"Blog","https://hilpcb.com/en/blog/",{"@type":56,"position":65,"name":35,"item":46},3,1793496913971]