[{"data":1,"prerenderedAt":65},["ShallowReactive",2],{"blog-smt-solder-bridge-prevention-en":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":29,"slug":34,"sourceLocale":35,"availableLocales":36,"jsonld":41},"Solder Bridges on SMT PCBs: Root Causes and Prevention Before Reflow","Isolate SMT solder bridging across stencil printing (3D SPI), component placement, and reflow stages. Fix fine-pitch QFP, QFN, and SOIC shorts without starving neighboring joints.","2026-10-27","technology","/assets/blogs/smt-solder-bridge-prevention/04-bridge-diagnostic-flow.svg",11,2004,"PT11M","\u003Cp>When post-reflow AOI flags a solder bridge across two adjacent SMT leads on a \u003Cspan class=\"math-inline\">0.4 mm\u003C/span> or \u003Cspan class=\"math-inline\">0.5 mm\u003C/span> pitch QFP, QFN, or connector, the most common floor-level mistake is immediately shrinking the stencil thickness or dropping reflow peak temperature. A post-reflow solder bridge is only the final solidified state—the unwanted connection could have formed \u003Cstrong>during stencil printing\u003C/strong>, \u003Cstrong>during pick-and-place compression\u003C/strong>, or \u003Cstrong>during reflow heating\u003C/strong>.\u003C/p>\n\u003Cp>Effective prevention starts by identifying the \u003Cstrong>earliest process stage\u003C/strong> where solder or paste crosses the inter-pad insulation gap, while verifying that any corrective adjustment does not starve neighboring components of solder volume. Note that this guide covers \u003Cstrong>visible SMT leads and perimeter pads\u003C/strong>; for hidden array balls beneath BGAs and LGAs, use our dedicated \u003Ca href=\"/en/blog/bga-soldering-defects/\">BGA soldering defects and X-ray guide\u003C/a>.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/blogs/smt-solder-bridge-prevention/04-bridge-diagnostic-flow.svg\" alt=\"Stage-gated SMT solder bridge diagnostic workflow across 3D SPI, pre-reflow placement AOI, and post-reflow inspection\">\u003C/p>\n\u003Ch2>1. Gate 0: Separate Electrical Shorts from Common-Net Workmanship Bridges\u003C/h2>\n\u003Cp>Before modifying stencil apertures or printer parameters, inspect the bridged pin pair against the \u003Cstrong>released CAD schematic netlist and solder-mask artwork\u003C/strong>:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Different Nets (True Electrical Short):\u003C/strong> If Pin 14 (\u003Ccode>VCC\u003C/code>) and Pin 15 (\u003Ccode>GND\u003C/code> or \u003Ccode>SDA\u003C/code>) are bridged by solder, the defect is both an IPC-A-610 workmanship reject and a hard electrical short that can damage components during power-up ICT/FCT.\u003C/li>\n\u003Cli>\u003Cstrong>Common Net (Same-Net Solder Bridge):\u003C/strong> High-current power ICs, QFN ground pins, and shielded connectors frequently assign two or more adjacent pins to the exact same net (\u003Ccode>GND\u003C/code> or \u003Ccode>SW\u003C/code>). If the PCB layout omitted the solder-mask web between those adjacent common-net pads (or tied them together with a wide copper flood between pads), molten solder will naturally coalesce across the unmasked copper.\u003Cul>\n\u003Cli>\u003Cstrong>Important Contract Boundary:\u003C/strong> Even when two bridged pins share the same electrical net and pass functional testing, \u003Cstrong>unintended solder bridging across separate component leads is still flagged as a workmanship defect under IPC-A-610\u003C/strong> unless the design drawing explicitly defines a shared/gang land pattern or a documented customer workmanship concession.\u003C/li>\n\u003C/ul>\n\u003C/li>\n\u003C/ol>\n\u003Ch2>2. Locating the Earliest Stage of Bridge Formation\u003C/h2>\n\u003Cp>As documented in \u003Ca href=\"https://smtnet.com/library/files/upload/Defect-Minimization.pdf\">Kester's SMT defect minimization guidelines\u003C/a> and \u003Ca href=\"https://www.indium.com/blog/stages-of-a-reflow-profile-part-i/\">Indium Corporation's reflow profile analysis\u003C/a>, solder bridging follows three distinct physical pathways depending on when the paste or solder first makes contact across the gap. Use matched, same-field-of-view inspection images from \u003Cstrong>3D SPI\u003C/strong>, \u003Cstrong>pre-reflow placement AOI\u003C/strong>, and \u003Cstrong>post-reflow AOI\u003C/strong> to isolate the active branch:\u003C/p>\n\u003Cp>\u003Cem>(Downloadable stage-gated troubleshooting matrix: \u003Ca href=\"/assets/blogs/smt-solder-bridge-prevention/04-solder-bridge-diagnostic.csv\">04-solder-bridge-diagnostic.csv\u003C/a>.)\u003C/em>\u003C/p>\n\u003Ch3>Branch A: Paste Deposits Are Already Connected After Printing (3D SPI)\u003C/h3>\n\u003Cp>If 3D SPI shows solder paste bridging the gap between adjacent pads before a component ever touches the board, the reflow oven is innocent. Investigate four printing mechanics (detailed in our \u003Ca href=\"/en/blog/solder-paste-inspection-spi/\">solder paste inspection (SPI) guide\u003C/a>):\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Poor Stencil-to-PCB Gasketing:\u003C/strong> If the PCB warps downward due to insufficient under-board support pins—or if a tall nearby silkscreen legend or thick copper trace holds the stencil foil slightly off the pads—squeegee pressure pumps paste underneath the stencil web ("underside bleed").\u003C/li>\n\u003Cli>\u003Cstrong>Infrequent Understencil Wiping:\u003C/strong> Dried or smeared paste clinging to the bottom of fine-pitch stencil webs transfers directly onto the solder mask dam on subsequent prints. Shortening the wet/vacuum/dry wipe interval (e.g., from every 10 prints to every 3–5 prints) immediately clears underside smearing.\u003C/li>\n\u003Cli>\u003Cstrong>Print Registration Offset:\u003C/strong> A global X/Y/\u003Cspan class=\"math-inline\">θ\u003C/span> fiducial alignment shift pushes printed paste bricks off the copper pads and onto the inter-pad solder mask web, where adjacent deposits touch or slump together.\u003C/li>\n\u003Cli>\u003Cstrong>Excessive Aperture Width on Fine Pitch:\u003C/strong> Printing \u003Cspan class=\"math-inline\">1:1\u003C/span> aperture-to-pad width on \u003Cspan class=\"math-inline\">0.4--0.5 mm\u003C/span> pitch gull-wing or QFN pads leaves minimal margin for print variation. Reducing aperture width by \u003Cstrong>5–10%\u003C/strong> (while maintaining aperture area ratio \u003Cspan class=\"math-inline\">AR = (W · L / 2(W+L)T) ≥ 0.66\u003C/span>) narrows the printed brick without sacrificing vertical release consistency.\u003C/li>\n\u003C/ul>\n\u003Ch3>Branch B: Paste Is Separate at SPI, But Connected Immediately After Placement\u003C/h3>\n\u003Cp>When 3D SPI confirms clean, separated rectangular paste bricks, yet pre-reflow AOI shows paste squeezed across the gap after pick-and-place mounting, the cause lies in \u003Cstrong>mechanical displacement during component seating\u003C/strong>:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Excessive Nozzle Z-Axis Force / Overtravel:\u003C/strong> If the component thickness in the pick-and-place package library is entered too small—or if Z-axis placement force is set too high without spring buffering—the component leads smash the paste bricks flat, extruding wet paste sideways across the gap.\u003C/li>\n\u003Cli>\u003Cstrong>Placement X/Y/\u003Cspan class=\"math-inline\">θ\u003C/span> Skew:\u003C/strong> Even a \u003Cspan class=\"math-inline\">0.05--0.08 mm\u003C/span> rotational or lateral placement offset on a \u003Cspan class=\"math-inline\">0.4 mm\u003C/span> pitch QFP places the metal lead edge into the gap between two paste deposits, creating a mechanical capillary bridge between both bricks.\u003C/li>\n\u003Cli>\u003Cstrong>QFN / LGA Center Thermal Pad Paste Squeeze-Out:\u003C/strong> Printing a solid 100% solder paste brick on a QFN's large central exposed thermal pad causes the package to float or compress excess molten solder outward into the surrounding perimeter signal pins. Always segment large thermal-pad stencil apertures into a \u003Cstrong>windowpane grid covering 50–70% of the pad area\u003C/strong>, leaving \u003Cspan class=\"math-inline\">0.25--0.40 mm\u003C/span> web channels for flux outgassing and planar seating.\u003C/li>\n\u003C/ul>\n\u003Ch3>Branch C: Paste Remains Separate After Placement, But Bridges During Reflow\u003C/h3>\n\u003Cp>When pre-reflow inspection proves the paste and leads are cleanly separated entering the oven, bridging occurs through \u003Cstrong>liquid-phase coalescence or thermal slump\u003C/strong>:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Missing or Narrow Solder Mask Dams (Web Slivers):\u003C/strong> Solder mask between fine-pitch pads acts as a physical non-wetting barrier. For LPI solder mask, maintain a minimum mask dam width of \u003Cstrong>\u003Cspan class=\"math-inline\">≥ 0.075--0.10 mm\u003C/span> (\u003Cspan class=\"math-inline\">3--4 mil\u003C/span>)\u003C/strong>. If CAD pad widths leave only a \u003Cspan class=\"math-inline\">0.03 mm\u003C/span> mask sliver, the fabricator's CAM team must strip the sliver to prevent flaking, leaving bare laminate (or exposed copper) where molten solder easily coalesces.\u003C/li>\n\u003Cli>\u003Cstrong>Thermal Slump During Preheat Ramp:\u003C/strong> Heating the assembly too rapidly during the initial preheat ramp (or using paste that has exceeded its stencil floor life or absorbed ambient humidity) causes the flux vehicle's viscosity to drop sharply before solvent evaporation completes. The softening paste slumps sideways across the gap before reaching liquidus (\u003Ca href=\"https://www.indium.com/blog/stages-of-a-reflow-profile-part-i/\">Indium Reflow Stages Part I\u003C/a>).\u003C/li>\n\u003C/ul>\n\u003Ch2>3. Why "Use Less Solder Everywhere" Breaks Mixed-Technology Boards\u003C/h2>\n\u003Cp>A common knee-jerk proposal when fine-pitch ICs bridge is stepping down the entire stencil foil thickness (for example, changing from \u003Cspan class=\"math-inline\">0.125 mm\u003C/span> / \u003Cspan class=\"math-inline\">5 mil\u003C/span> to \u003Cspan class=\"math-inline\">0.080 mm\u003C/span> / \u003Cspan class=\"math-inline\">3.2 mil\u003C/span> across the whole panel). While thinner foil reduces paste volume on the bridging QFP, it simultaneously cuts solder volume by \u003Cspan class=\"math-inline\">36%\u003C/span> on every large inductor, power MOSFET, and SMD connector on the board—causing \u003Cstrong>open solder joints, insufficient heel fillets, and failed coplanarity\u003C/strong> on larger packages.\u003C/p>\n\u003Cp>Before approving any corrective action, evaluate the required counter-check across the entire assembly:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Candidate Corrective Action\u003C/th>\n\u003Cth>When It Is Justified\u003C/th>\n\u003Cth>Mandatory Counter-Check Before Production Sign-Off\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Local Aperture Width Reduction (5–10%) or Staggered Tooth Pattern\u003C/strong>\u003C/td>\n\u003Ctd>Bridging restricted to specific \u003Cspan class=\"math-inline\">0.4--0.5 mm\u003C/span> pitch QFP/QFN/connector footprints\u003C/td>\n\u003Ctd>Check that aperture Area Ratio stays \u003Cspan class=\"math-inline\">≥ 0.66\u003C/span> on 3D SPI and post-reflow joints meet IPC-A-610 minimum heel/side fillet height\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Step-Down Stencil (\u003Cspan class=\"math-inline\">0.125 mm\u003C/span> main / \u003Cspan class=\"math-inline\">0.100 mm\u003C/span> local cavity)\u003C/strong>\u003C/td>\n\u003Ctd>Mixed-technology board combining large power connectors with \u003Cspan class=\"math-inline\">0.4 mm\u003C/span> fine-pitch or 0201/01005 parts\u003C/td>\n\u003Ctd>Verify keepout distance around the step cavity (\u003Cspan class=\"math-inline\">3--5 mm\u003C/span>) so neighbouring pads still gasket cleanly under the squeegee\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Calibrate Placement Z-Height & Vision Alignment\u003C/strong>\u003C/td>\n\u003Ctd>Pre-reflow AOI confirms paste squeeze-out or lead skew after placement\u003C/td>\n\u003Ctd>Inspect 100% of pins on the package to confirm slightly lighter Z-force does not leave lifted/unseated leads (coplanarity opens)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Adjust Reflow Preheat Ramp & Soak Window\u003C/strong>\u003C/td>\n\u003Ctd>Post-placement paste is clean, but thermal slump bridges pads during oven entry\u003C/td>\n\u003Ctd>Verify with board-mounted thermocouples that peak temperature and time-above-liquidus (TAL) remain within limits for all heat-sensitive components\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Restore Solder Mask Dam (\u003Cspan class=\"math-inline\">≥ 0.075 mm\u003C/span>) in CAD\u003C/strong>\u003C/td>\n\u003Ctd>Bare-board inspection shows missing mask webs between fine-pitch pads\u003C/td>\n\u003Ctd>Confirm updated pad width still satisfies component toe/heel land pattern requirements\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>4. Worked NPI Case: Stopping Recurring Bridging Without Changing the Reflow Recipe\u003C/h2>\n\u003Cp>On a pilot run of an industrial controller board, post-reflow AOI flags recurring solder bridges between pins 22–28 on \u003Ccode>U4\u003C/code> (a \u003Cspan class=\"math-inline\">0.4 mm\u003C/span> pitch, 64-pin LQFP). The line operator suggests lowering the reflow peak temperature from \u003Cspan class=\"math-inline\">242°C\u003C/span> to \u003Cspan class=\"math-inline\">232°C\u003C/span>.\u003C/p>\n\u003Cp>Before touching the oven recipe—which is already optimized for a high-thermal-mass BGA (\u003Ccode>U1\u003C/code>) on the same board—the process engineer checks the stage records for \u003Ccode>U4\u003C/code>:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>3D SPI Review:\u003C/strong> Shows paste bricks on \u003Ccode>U4\u003C/code> pins 22–28 are already touching along the inner edge of the footprint before placement, with deposit heights reading \u003Cspan class=\"math-inline\">145%\u003C/span> of foil thickness and a \u003Cspan class=\"math-inline\">-0.04 mm\u003C/span> Y-offset.\u003C/li>\n\u003Cli>\u003Cstrong>Printer & Stencil Inspection:\u003C/strong> Reveals that an unpopulated silkscreen component outline box was printed directly between the \u003Ccode>U4\u003C/code> pad rows, lifting the stencil foil by \u003Cspan class=\"math-inline\">18 μm\u003C/span> and preventing a flush gasket seal.\u003C/li>\n\u003Cli>\u003Cstrong>Controlled Fix & Verification:\u003C/strong> The team increases understencil wet-wipe frequency, applies a \u003Cspan class=\"math-inline\">0.03 mm\u003C/span> inner-edge aperture reduction on \u003Ccode>U4\u003C/code>'s stencil pads for the pilot lot, and issues a PCB DFM change to clip the silkscreen away from the \u003Ccode>U4\u003C/code> pad row by \u003Cspan class=\"math-inline\">≥ 0.15 mm\u003C/span>. On the 30-board verification run, 3D SPI confirms 100% separated paste deposits (\u003Cspan class=\"math-inline\">92--104%\u003C/span> volume) and post-reflow AOI verifies zero bridges and compliant IPC-A-610 gull-wing heel fillets—while leaving \u003Ccode>U1\u003C/code>'s BGA reflow profile completely untouched.\u003C/li>\n\u003C/ol>\n\u003Ch2>5. What to Submit for an SMT Assembly DFM and Bridging Review\u003C/h2>\n\u003Cp>To prevent fine-pitch solder bridging before stencils are cut, include the following in your \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a> package:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Gerber / ODB++ Layers (Copper, Solder Mask, Paste, Silkscreen):\u003C/strong> Allowing CAM and SMT engineers to verify solder-mask dam widths (\u003Cspan class=\"math-inline\">≥ 0.075 mm\u003C/span>), silkscreen-to-pad clearances, and QFN thermal-pad via plugging.\u003C/li>\n\u003Cli>\u003Cstrong>Complete BOM and Component Package Drawings:\u003C/strong> So engineering can cross-check \u003Cspan class=\"math-inline\">0.4 mm\u003C/span> / \u003Cspan class=\"math-inline\">0.35 mm\u003C/span> fine-pitch lead widths, QFN exposed-pad dimensions, and step-stencil requirements.\u003C/li>\n\u003Cli>\u003Cstrong>Defect Map & Stage Evidence (For Troubleshooting Existing Builds):\u003C/strong> Provide annotated photos, designator/pin numbers, netlist status, and any available 3D SPI or AOI logs, along with \u003Ca href=\"/assets/blogs/smt-solder-bridge-prevention/04-solder-bridge-diagnostic.csv\">04-solder-bridge-diagnostic.csv\u003C/a>.\u003C/li>\n\u003C/ul>\n\u003Cp>HILPCB's \u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a> and \u003Ca href=\"/en/products/turnkey-assembly/\">turnkey PCB assembly\u003C/a> lines combine upfront stencil aperture DFM (including laser-cut nano-coated and step stencils, plus automated QFN windowpane segmentation) with \u003Cstrong>100% inline 3D SPI\u003C/strong> and \u003Cstrong>multi-angle 2D/3D AOI\u003C/strong> to catch print and placement anomalies before boards ever enter the reflow oven. Upload your design files to \u003Ca href=\"/en/quote/\">request a quote\u003C/a> and receive an engineering DFM review.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>What is the minimum solder mask dam (web) width needed to prevent SMT solder bridging?\u003C/h3>\n\u003Cp>For standard liquid photoimageable (LPI) green solder mask, maintain at least \u003Cstrong>\u003Cspan class=\"math-inline\">0.075 mm\u003C/span> to \u003Cspan class=\"math-inline\">0.10 mm\u003C/span> (\u003Cspan class=\"math-inline\">3--4 mil\u003C/span>)\u003C/strong> of uninterrupted mask web between adjacent copper pads. Below \u003Cspan class=\"math-inline\">0.075 mm\u003C/span> (or slightly wider for white/black solder masks), the thin mask sliver cannot adhere reliably during developing and will be removed by CAM, leaving bare dielectric between fine-pitch pads.\u003C/p>\n\u003Ch3>Why do QFN packages often bridge between the center thermal pad and the outer signal pins?\u003C/h3>\n\u003Cp>If the stencil aperture for the QFN's central exposed thermal pad is cut at \u003Cspan class=\"math-inline\">1:1\u003C/span> (\u003Cspan class=\"math-inline\">100%\u003C/span> coverage), too much solder paste is deposited underneath the package. During reflow, flux outgassing and package weight squeeze excess molten solder outward across the narrow gap into the perimeter pins. Segmenting the thermal-pad stencil aperture into a \u003Cstrong>windowpane grid with 50%–70% total paste coverage\u003C/strong> prevents both perimeter bridging and package floating.\u003C/p>\n\u003Ch3>If a solder bridge connects two pins that are both grounded (same net), can it be shipped as-is?\u003C/h3>\n\u003Cp>Electrically, a bridge between two common-net \u003Ccode>GND\u003C/code> pins will not cause a short circuit. However, under \u003Cstrong>IPC-A-610 workmanship standards\u003C/strong>, an unplanned solder bridge connecting separate component leads or discrete lands is still classified as a defect unless the PCB footprint was intentionally designed as a shared gang land or the customer grants an explicit written workmanship concession.\u003C/p>\n\u003Ch3>Should operators hand-rework fine-pitch solder bridges immediately at the end of the line?\u003C/h3>\n\u003Cp>No. Always log the exact reference designator, pin pair, and panel location—and check whether 3D SPI and pre-reflow AOI images exist for that board—before touching the joint with a soldering iron and wick. Immediate unlogged touch-up destroys the physical evidence needed to correct a drifting stencil wipe cycle or placement offset, while adding localized thermal and flux-residue risks to the fine-pitch IC.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Related\">\u003Ch3>Related links\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/en/blog/bga-soldering-defects/\">BGA Soldering Defects Guide and Quality Control Methods\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/smt-solder-bridge-prevention/04-solder-bridge-diagnostic.csv\">04-solder-bridge-diagnostic.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/blog/solder-paste-inspection-spi/\">What Is Solder Paste Inspection (SPI)? Measurements and Print Release\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/smt-assembly/\">SMT assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/products/turnkey-assembly/\">turnkey PCB assembly\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/en/quote/\">request a quote\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,18,22,26],{"question":15,"answer":16,"answerText":17},"What is the minimum solder mask dam (web) width needed to prevent SMT solder bridging?","For standard liquid photoimageable (LPI) green solder mask, maintain at least **$0.075\\text{ mm}$ to $0.10\\text{ mm}$ ($3\\text{--}4\\text{ mil}$)** of uninterrupted mask web between adjacent copper pads. Below $0.075\\text{ mm}$ (or slightly wider for white/black solder masks), the thin mask sliver cannot adhere reliably during developing and will be removed by CAM, leaving bare dielectric between fine-pitch pads.","For standard liquid photoimageable (LPI) green solder mask, maintain at least $0.075\\text{ mm}$ to $0.10\\text{ mm}$ ($3\\text{--}4\\text{ mil}$) of uninterrupted mask web between adjacent copper pads. Below $0.075\\text{ mm}$ (or slightly wider for white/black solder masks), the thin mask sliver cannot adhere reliably during developing and will be removed by CAM, leaving bare dielectric between fine-pitch pads.",{"question":19,"answer":20,"answerText":21},"Why do QFN packages often bridge between the center thermal pad and the outer signal pins?","If the stencil aperture for the QFN's central exposed thermal pad is cut at $1:1$ ($100\\%$ coverage), too much solder paste is deposited underneath the package. During reflow, flux outgassing and package weight squeeze excess molten solder outward across the narrow gap into the perimeter pins. Segmenting the thermal-pad stencil aperture into a **windowpane grid with 50%–70% total paste coverage** prevents both perimeter bridging and package floating.","If the stencil aperture for the QFN's central exposed thermal pad is cut at $1:1$ ($100%$ coverage), too much solder paste is deposited underneath the package. During reflow, flux outgassing and package weight squeeze excess molten solder outward across the narrow gap into the perimeter pins. Segmenting the thermal-pad stencil aperture into a windowpane grid with 50%–70% total paste coverage prevents both perimeter bridging and package floating.",{"question":23,"answer":24,"answerText":25},"If a solder bridge connects two pins that are both grounded (same net), can it be shipped as-is?","Electrically, a bridge between two common-net `GND` pins will not cause a short circuit. However, under **IPC-A-610 workmanship standards**, an unplanned solder bridge connecting separate component leads or discrete lands is still classified as a defect unless the PCB footprint was intentionally designed as a shared gang land or the customer grants an explicit written workmanship concession.","Electrically, a bridge between two common-net GND pins will not cause a short circuit. However, under IPC-A-610 workmanship standards, an unplanned solder bridge connecting separate component leads or discrete lands is still classified as a defect unless the PCB footprint was intentionally designed as a shared gang land or the customer grants an explicit written workmanship concession.",{"question":27,"answer":28,"answerText":28},"Should operators hand-rework fine-pitch solder bridges immediately at the end of the line?","No. Always log the exact reference designator, pin pair, and panel location—and check whether 3D SPI and pre-reflow AOI images exist for that board—before touching the joint with a soldering iron and wick. Immediate unlogged touch-up destroys the physical evidence needed to correct a drifting stencil wipe cycle or placement offset, while adding localized thermal and flux-residue risks to the fine-pitch IC.",[30,31,32,33],"solder bridge","SMT solder bridging","stencil aperture design","solder mask dam","smt-solder-bridge-prevention","en",[35,37,38,39,40],"de","cn","fr","ru",{"blog":42,"breadcrumb":51},{"@context":43,"@type":44,"headline":4,"description":5,"image":8,"url":45,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":46,"articleSection":7,"author":47,"publisher":50},"https://schema.org","BlogPosting","https://hilpcb.com/en/blog/smt-solder-bridge-prevention/","solder bridge, SMT solder bridging, stencil aperture design, solder mask dam",{"@type":48,"name":49},"Organization","HILPCB",{"@type":48,"name":49},{"@context":43,"@type":52,"itemListElement":53},"BreadcrumbList",[54,59,63],{"@type":55,"position":56,"name":57,"item":58},"ListItem",1,"Home","https://hilpcb.com/",{"@type":55,"position":60,"name":61,"item":62},2,"Blog","https://hilpcb.com/en/blog/",{"@type":55,"position":64,"name":34,"item":45},3,1793496914010]