[{"data":1,"prerenderedAt":63},["ShallowReactive",2],{"blog-pcb-annular-ring-design-it":3},{"title":4,"description":5,"date":6,"lastUpdated":6,"category":7,"image":8,"readingTime":9,"wordCount":10,"timeRequired":11,"htmlContent":12,"faq":13,"tags":27,"slug":32,"sourceLocale":33,"availableLocales":34,"jsonld":39},"PCB Annular Ring: Pad Size, Drill Reference and Breakout Checks","Calculate PCB annular ring margins across outer and inner layers, separate tool-size from finished-hole references, and evaluate breakout, teardrops, and clearance tradeoffs.","2026-10-26","technology","/assets/blogs/pcb-annular-ring-design/layer-margin-before-after.svg",14,2617,"PT14M","\u003Cp>When a via or component pad fails a fabrication DFM check for insufficient annular ring, the discrepancy usually starts with an unstated reference boundary: did the layout engineer subtract the \u003Cstrong>finished hole diameter\u003C/strong> from the pad diameter while the fabricator's CAM rule subtracted the \u003Cstrong>compensated production drill diameter\u003C/strong>? Because plated through-holes are drilled larger than their finished opening to accommodate electroless copper, electrolytic barrel plating, and surface finish, those two equations yield different radial ring widths on the exact same CAD padstack.\u003C/p>\n\u003Cp>Resolving annular ring margin before release requires three engineering steps: locking the hole-reference boundary with the fabricator, evaluating inner layers separately from outer layers to account for lamination registration shift, and checking that any pad enlargement does not violate adjacent trace or plane clearances. For broader pre-release verification across trace/space, aspect ratio, and netlist checks, see our \u003Ca href=\"/it/blog/what-is-dfm-design-for-manufacturing/\">PCB DFM review guide\u003C/a>.\u003C/p>\n\u003Cp>\u003Cimg src=\"/assets/blogs/pcb-annular-ring-design/layer-margin-before-after.svg\" alt=\"Inner-layer L2 annular ring tolerance stackup and adjacent copper clearance tradeoff\">\u003C/p>\n\u003Ch2>1. Tool Reference vs. Finished-Hole Reference: Why Two Correct Equations Disagree\u003C/h2>\n\u003Cp>An annular ring is the width of copper land remaining around a drilled hole. On an ideal concentric padstack, the nominal radial width is half the diameter difference between the copper pad and the hole reference:\u003C/p>\n\u003Cdiv class=\"math-block\">Nominal Annular Ring  (W\u003Csub>nom\u003C/sub>) = (D\u003Csub>pad\u003C/sub> - D\u003Csub>ref\u003C/sub>/ 2)\u003C/div>\n\n\u003Cp>In PCB design and inspection, however, \u003Cspan class=\"math-inline\">D\u003Csub>ref\u003C/sub>\u003C/span> is defined in two distinct ways depending on whether you are running a \u003Cstrong>pre-production CAM design rule check\u003C/strong> or \u003Cstrong>inspecting a finished board\u003C/strong>:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Tool-Size Design Reference (\u003Cspan class=\"math-inline\">D\u003Csub>ref\u003C/sub> = D\u003Csub>tool\u003C/sub>\u003C/span>):\u003C/strong> Many bare-board fabricators evaluate incoming CAD annular ring rules against the \u003Cstrong>production drill bit diameter\u003C/strong> (\u003Cspan class=\"math-inline\">D\u003Csub>tool\u003C/sub>\u003C/span>) rather than the finished plated hole size. As documented in fabricators' published drill-classification and design rules, the drill bit physically cuts away the copper foil on both outer and inner layers. If a \u003Cspan class=\"math-inline\">0.30 mm\u003C/span> finished via is drilled with a \u003Cspan class=\"math-inline\">0.40 mm\u003C/span> production tool inside a \u003Cspan class=\"math-inline\">0.60 mm\u003C/span> pad, the nominal copper ring left around the drill bit is \u003Cspan class=\"math-inline\">(0.60 - 0.40)/2 = 0.10 mm\u003C/span>, not the \u003Cspan class=\"math-inline\">(0.60 - 0.30)/2 = 0.15 mm\u003C/span> displayed in a CAD tool set to finished hole size.\u003C/li>\n\u003Cli>\u003Cstrong>Finished Inspection Reference (External vs. Internal Lands):\u003C/strong> During final quality inspection (such as metallographic cross-sectioning or optical inspection under IPC-6012 / IPC-A-600), \u003Cstrong>external annular ring\u003C/strong> is measured from the inside surface of the plated hole wall (or edge of the hole on non-plated holes) to the outer edge of the surface pad, whereas \u003Cstrong>internal annular ring\u003C/strong> is measured from the edge of the drilled hole wall to the outer edge of the internal copper land. Crucially, barrel copper plated inside the hole wall adds axial strength and electrical continuity, but \u003Cstrong>plating does not restore internal capture-pad copper that was already severed by the drill bit\u003C/strong>.\u003C/li>\n\u003C/ol>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Dimension in the Padstack\u003C/th>\n\u003Cth>Physical Meaning in Fabrication\u003C/th>\n\u003Cth>Typical Impact on Annular Ring Calculation\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>Finished Hole Size (\u003Cspan class=\"math-inline\">D\u003Csub>FHS\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>Clear inner diameter after barrel copper plating and surface finish (HASL, ENIG, etc.)\u003C/td>\n\u003Ctd>Controls component pin fit or via opening; overstates available drill-to-pad margin if used directly in inner-layer ring equations\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Production Drill Diameter (\u003Cspan class=\"math-inline\">D\u003Csub>tool\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>Actual mechanical drill bit or laser aperture diameter used by CAM to achieve \u003Cspan class=\"math-inline\">D\u003Csub>FHS\u003C/sub>\u003C/span>\u003C/td>\n\u003Ctd>Directly determines how much copper land is removed when the hole is drilled through the stackup\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Released Pad Diameter (\u003Cspan class=\"math-inline\">D\u003Csub>pad\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>Copper land diameter on the specific layer in Gerber / ODB++ / IPC-2581 artwork\u003C/td>\n\u003Ctd>Outer pads, inner signal pads, and plane thermal-relief pads may have different diameters on the same hole\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>Finished Etched Pad (\u003Cspan class=\"math-inline\">D\u003Csub>pad,min\u003C/sub>\u003C/span>)\u003C/strong>\u003C/td>\n\u003Ctd>Actual copper diameter remaining after outer/inner imaging and chemical etching\u003C/td>\n\u003Ctd>Lateral etch undercut reduces the effective land radius available to absorb drill offset\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch2>2. Why Inner Layers Fail First: Lamination Movement and Registration Stackup\u003C/h2>\n\u003Cp>A padstack that passes comfortably on Layer 1 and Layer \u003Cspan class=\"math-inline\">N\u003C/span> frequently fails on internal signal layers (L2, L3, etc.). Outer layers are imaged \u003Cstrong>after\u003C/strong> mechanical through-hole drilling, allowing direct optical alignment (LDI) to fiducials drilled in the same setup. Inner layers, by contrast, are etched onto individual cores \u003Cstrong>before\u003C/strong> lamination and drilling, exposing them to three cumulative positional error sources:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Lamination Scale and Non-Linear Material Movement:\u003C/strong> During high-temperature, high-pressure lamination cycles, prepreg resin flows and glass-reinforced cores expand, contract, and relax non-uniformly along the warp and weft directions of the glass cloth. Even with core-specific scale compensation factors applied in CAM, residual dimensional variance remains.\u003C/li>\n\u003Cli>\u003Cstrong>Layer-to-Layer Alignment Tolerance:\u003C/strong> Optical or X-ray registration aligns multiple etched cores prior to pressing, introducing core-to-core alignment tolerances (a tolerance that major fabricators publish in their design rules).\u003C/li>\n\u003Cli>\u003Cstrong>Mechanical Drill Runout (Wander):\u003C/strong> As a small mechanical drill bit penetrates a thick multilayer board or high-glass-content laminate, glass bundles deflect the bit tip laterally, increasing positional error at deeper internal layers.\u003C/li>\n\u003C/ul>\n\u003Cp>To evaluate whether a padstack can survive fabrication without unintended breakout, separate \u003Cstrong>dimensional loss\u003C/strong> (pad etch reduction and tool enlargement) from \u003Cstrong>relative radial center offset\u003C/strong> (\u003Cspan class=\"math-inline\">Δ r\u003C/span>):\u003C/p>\n\u003Cdiv class=\"math-block\">W\u003Csub>\\min\u003C/sub> = (D\u003Csub>pad,min\u003C/sub> - D\u003Csub>tool,max\u003C/sub>/ 2) - Δ r\u003Csub>\\max\u003C/sub>\u003C/div>\n\n\u003Cp>Note that \u003Cspan class=\"math-inline\">Δ r\u003Csub>\\max\u003C/sub>\u003C/span> represents the \u003Cstrong>combined radial center-to-center offset\u003C/strong> between the etched pad and the drilled hole on that specific layer. If a fabricator provides a consolidated registration allowance that already accounts for core movement and drill accuracy, do not subtract a second separate drill tolerance on top of it.\u003C/p>\n\u003Ch3>Worked Layer-by-Layer Tolerance Stackup (L1 vs. L2 vs. L4)\u003C/h3>\n\u003Cp>Consider a 4-layer board reviewed against an illustrative project minimum of \u003Cspan class=\"math-inline\">0.10 mm\u003C/span> remaining radial ring. The outer pads (L1, L4) are designed at \u003Cspan class=\"math-inline\">0.80 mm\u003C/span> nominal diameter, while the inner signal pad (L2) was reduced to \u003Cspan class=\"math-inline\">0.70 mm\u003C/span> to route an adjacent trace:\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Layer & Scenario\u003C/th>\n\u003Cth align=\"right\">Nominal Pad (\u003Cspan class=\"math-inline\">D\u003Csub>pad\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Etch Loss (\u003Cspan class=\"math-inline\">Δ D\u003Csub>etch\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Min Pad (\u003Cspan class=\"math-inline\">D\u003Csub>pad,min\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Max Tool (\u003Cspan class=\"math-inline\">D\u003Csub>tool,max\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Radial Offset (\u003Cspan class=\"math-inline\">Δ r\u003Csub>\\max\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Nominal Ring (\u003Cspan class=\"math-inline\">W\u003Csub>nom\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth align=\"right\">Worst-Case Min Ring (\u003Cspan class=\"math-inline\">W\u003Csub>\\min\u003C/sub>\u003C/span>)\u003C/th>\n\u003Cth>Engineering Disposition\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cstrong>L1 Outer (Baseline)\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">0.80 mm\u003C/td>\n\u003Ctd align=\"right\">0.04 mm\u003C/td>\n\u003Ctd align=\"right\">0.76 mm\u003C/td>\n\u003Ctd align=\"right\">0.42 mm\u003C/td>\n\u003Ctd align=\"right\">0.05 mm\u003C/td>\n\u003Ctd align=\"right\">0.200 mm\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.120 mm\u003C/strong>\u003C/td>\n\u003Ctd>Passes 0.100 mm target (+0.020 mm margin)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L4 Outer (Baseline)\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">0.80 mm\u003C/td>\n\u003Ctd align=\"right\">0.04 mm\u003C/td>\n\u003Ctd align=\"right\">0.76 mm\u003C/td>\n\u003Ctd align=\"right\">0.42 mm\u003C/td>\n\u003Ctd align=\"right\">0.06 mm\u003C/td>\n\u003Ctd align=\"right\">0.200 mm\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.110 mm\u003C/strong>\u003C/td>\n\u003Ctd>Passes 0.100 mm target (+0.010 mm margin)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L2 Inner (Baseline)\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">0.70 mm\u003C/td>\n\u003Ctd align=\"right\">0.04 mm\u003C/td>\n\u003Ctd align=\"right\">0.66 mm\u003C/td>\n\u003Ctd align=\"right\">0.42 mm\u003C/td>\n\u003Ctd align=\"right\">0.07 mm\u003C/td>\n\u003Ctd align=\"right\">0.150 mm\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.050 mm\u003C/strong>\u003C/td>\n\u003Ctd>\u003Cstrong>Fails\u003C/strong> 0.100 mm target (−0.050 mm shortfall)\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L2 Option A (Enlarge Pad)\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">0.80 mm\u003C/td>\n\u003Ctd align=\"right\">0.04 mm\u003C/td>\n\u003Ctd align=\"right\">0.76 mm\u003C/td>\n\u003Ctd align=\"right\">0.42 mm\u003C/td>\n\u003Ctd align=\"right\">0.07 mm\u003C/td>\n\u003Ctd align=\"right\">0.200 mm\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.100 mm\u003C/strong>\u003C/td>\n\u003Ctd>Meets 0.100 mm target; \u003Cstrong>check neighbor spacing\u003C/strong>\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cstrong>L2 Option B (Smaller Tool)\u003C/strong>\u003C/td>\n\u003Ctd align=\"right\">0.70 mm\u003C/td>\n\u003Ctd align=\"right\">0.04 mm\u003C/td>\n\u003Ctd align=\"right\">0.66 mm\u003C/td>\n\u003Ctd align=\"right\">0.32 mm\u003C/td>\n\u003Ctd align=\"right\">0.07 mm\u003C/td>\n\u003Ctd align=\"right\">0.200 mm\u003C/td>\n\u003Ctd align=\"right\">\u003Cstrong>0.100 mm\u003C/strong>\u003C/td>\n\u003Ctd>Meets 0.100 mm target; \u003Cstrong>check hole aspect ratio / fit\u003C/strong>\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Cp>\u003Cem>(Full editable dataset: \u003Ca href=\"/assets/blogs/pcb-annular-ring-design/layer-margin-example.csv\">layer-margin-example.csv\u003C/a> and \u003Ca href=\"/assets/blogs/pcb-annular-ring-design/change-tradeoffs.csv\">change-tradeoffs.csv\u003C/a>.)\u003C/em>\u003C/p>\n\u003Cp>Inspecting only a top-layer CAD screenshot shows a \u003Cspan class=\"math-inline\">0.200 mm\u003C/span> nominal ring and a \u003Cspan class=\"math-inline\">0.120 mm\u003C/span> worst-case outer ring, completely hiding the \u003Cspan class=\"math-inline\">0.050 mm\u003C/span> inner-layer shortfall on L2.\u003C/p>\n\u003Ch3>Evaluating the Tradeoff: Pad Enlargement vs. Adjacent Copper Spacing\u003C/h3>\n\u003Cp>When L2 fails the ring budget, neither Option A nor Option B can be approved in isolation:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Consequence of Option A (Enlarging L2 Pad from 0.70 mm to 0.80 mm):\u003C/strong> Suppose an adjacent L2 signal trace edge sits at a fixed radial distance of \u003Cspan class=\"math-inline\">r = 0.55 mm\u003C/span> from the hole center. Increasing the nominal L2 pad diameter from \u003Cspan class=\"math-inline\">0.70 mm\u003C/span> (\u003Cspan class=\"math-inline\">r\u003Csub>pad\u003C/sub> = 0.35 mm\u003C/span>) to \u003Cspan class=\"math-inline\">0.80 mm\u003C/span> (\u003Cspan class=\"math-inline\">r\u003Csub>pad\u003C/sub> = 0.40 mm\u003C/span>) reduces the nominal pad-to-trace edge clearance from \u003Cspan class=\"math-inline\">0.55 - 0.35 = 0.20 mm\u003C/span> down to \u003Cspan class=\"math-inline\">0.55 - 0.40 = 0.15 mm\u003C/span>. Before approving the pad increase, confirm that \u003Cspan class=\"math-inline\">0.15 mm\u003C/span> (\u003Cspan class=\"math-inline\">6 mil\u003C/span>) satisfies your inner-layer copper weight etch rules, dielectric breakdown spacing, and crosstalk budget.\u003C/li>\n\u003Cli>\u003Cstrong>Consequence of Option B (Reducing Max Tool from 0.42 mm to 0.32 mm):\u003C/strong> If the hole is an interconnect via, dropping the drill size increases the hole aspect ratio (board thickness divided by drill diameter), which can push a thick board beyond standard plating throwing power. If the hole is a component PTH, reducing the drill changes the finished opening and can prevent component lead insertion (covered in detail in our \u003Ca href=\"/it/blog/pcb-finished-hole-size-drill-tolerance/\">finished hole size and drill tolerance guide\u003C/a>).\u003C/li>\n\u003C/ul>\n\u003Ch2>3. Tangency, Breakout, Teardrops, and Non-Functional Pads (NFPs)\u003C/h2>\n\u003Cp>When drill offset equals the available radial copper margin, the hole edge touches the outer boundary of the pad (\u003Cstrong>tangency\u003C/strong>, \u003Cspan class=\"math-inline\">W\u003Csub>\\min\u003C/sub> = 0\u003C/span>). If the offset exceeds that margin, the hole extends outside the pad boundary (\u003Cstrong>annular ring breakout\u003C/strong>, \u003Cspan class=\"math-inline\">W\u003Csub>\\min\u003C/sub> < 0\u003C/span>).\u003C/p>\n\u003Cp>Whether tangency or limited breakout is acceptable depends on the governing contractual standard and product class (see \u003Ca href=\"/it/blog/ipc-class-1-2-3/\">IPC Class 1 vs. Class 2 vs. Class 3 criteria\u003C/a>):\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>High-Reliability / Class 3 Builds:\u003C/strong> Typically require a continuous external and internal annular ring (e.g., \u003Cspan class=\"math-inline\">≥ 0.050 mm\u003C/span> external and \u003Cspan class=\"math-inline\">≥ 0.025 mm\u003C/span> internal minimum copper land) with no breakout permitted, ensuring 360° structural anchoring of the plated barrel under thermal cycling.\u003C/li>\n\u003Cli>\u003Cstrong>Dedicated-Service / Class 2 Builds:\u003C/strong> Commonly permit limited 90° breakout on vias or lands provided the conductor-to-land junction is never reduced below the minimum allowed trace width and the breakout does not violate minimum electrical spacing to adjacent nets.\u003C/li>\n\u003Cli>\u003Cstrong>Why Teardrops Are Essential at Trace Entry:\u003C/strong> Even where 90° breakout is contractually allowed, breakout occurring \u003Cstrong>at the exact angle where a narrow trace joins the pad\u003C/strong> can sever the circuit or create a high-resistance neck. Adding \u003Cstrong>teardrop fillets\u003C/strong> tapers the copper transition at the trace-to-pad junction, providing extra radial copper along the connected vector without enlarging the entire circular pad across tight BGA escape channels.\u003C/li>\n\u003Cli>\u003Cstrong>Non-Functional Pads (NFPs) on Inner Layers:\u003C/strong> On high-layer-count boards, vias often pass through internal signal layers where they have no electrical connection. Removing unconnected inner-layer NFPs eliminates the risk of inner-layer breakout on unconnected layers, reduces parasitic via capacitance on high-speed SerDes channels, and reduces drill wear—provided the fabricator confirms that NFP removal does not destabilize local copper balance or hole-wall desmear quality.\u003C/li>\n\u003C/ul>\n\u003Ch2>4. Reviewing Padstacks Across Special Geometries and Via Structures\u003C/h2>\n\u003Cp>A single circular equation does not cover every feature on a modern multilayer PCB. During pre-release review, audit these four geometry cases explicitly:\u003C/p>\n\u003Col>\n\u003Cli>\u003Cstrong>Plated Slots and Oblong Pads:\u003C/strong> A routed plated slot has straight sides and semi-circular ends. Evaluate annular ring along the full contour—both laterally (\u003Cspan class=\"math-inline\">W\u003Csub>pad\u003C/sub> - W\u003Csub>slot\u003C/sub>\u003C/span>) and longitudinally (\u003Cspan class=\"math-inline\">L\u003Csub>pad\u003C/sub> - L\u003Csub>slot\u003C/sub>\u003C/span>)—accounting for mechanical routing cutter tolerances rather than standard twist-drill tolerances.\u003C/li>\n\u003Cli>\u003Cstrong>Laser Microvias and Stacked/Staggered HDI Structures:\u003C/strong> In sequential build-up HDI stacks, a laser microvia (typically \u003Cspan class=\"math-inline\">0.05--0.125 mm\u003C/span> diameter) lands on an internal \u003Cstrong>target pad\u003C/strong> rather than passing through it. The critical check is both the top \u003Cstrong>capture pad\u003C/strong> ring and the bottom \u003Cstrong>target land\u003C/strong> containment so the laser beam never ablates into the underlying dielectric outside the target copper pad.\u003C/li>\n\u003Cli>\u003Cstrong>Via-in-Pad Plated Over (VIPPO):\u003C/strong> When vias are placed directly inside fine-pitch BGA or QFN SMD pads, verify the resin/copper fill and planarized cap specification using the \u003Ca href=\"/it/blog/via-filling-material-guide-pcb-stackup-materials/\">via-filling material guide\u003C/a> alongside the drill-to-pad margin.\u003C/li>\n\u003Cli>\u003Cstrong>Anti-Pad Clearances on Internal Planes:\u003C/strong> When you enlarge a via's internal capture pad on L2, verify whether the anti-pad opening on adjacent power/ground planes (L3, L5) must also expand to prevent plane-to-barrel shorts during drill wander.\u003C/li>\n\u003C/ol>\n\u003Ch2>5. Evaluating Supplier DFM Feedback and Submitting the Release Package\u003C/h2>\n\u003Cp>When a fabricator flags an annular ring exception during CAM preflight, require a specific, bounded engineering query (EQ) rather than a vague request to "accept CAM optimization":\u003C/p>\n\u003Ctable>\n\u003Cthead>\n\u003Ctr>\n\u003Cth>Fabricator EQ Response Style\u003C/th>\n\u003Cth>What It Tells Engineering\u003C/th>\n\u003Cth>Required Follow-Up Before Sign-Off\u003C/th>\n\u003C/tr>\n\u003C/thead>\n\u003Ctbody>\u003Ctr>\n\u003Ctd>\u003Cem>"Annular ring is tight; please confirm we can modify working files as needed."\u003C/em>\u003C/td>\n\u003Ctd>Unbounded request; does not state which layers, nets, hole sizes, or clearances will change\u003C/td>\n\u003Ctd>\u003Cstrong>Reject blanket permission.\u003C/strong> Ask for the exact drill tool table, affected layer list, and marked before/after Gerber overlay\u003C/td>\n\u003C/tr>\n\u003Ctr>\n\u003Ctd>\u003Cem>"Via group D04 (0.25 mm FHS / 0.35 mm tool) has 0.05 mm nominal ring on L2/L5. Propose enlarging L2/L5 connected pads from 0.45 mm to 0.50 mm and removing unconnected NFPs; minimum L2 trace-to-pad space becomes 0.11 mm (see attached overlay CAM-B1)."\u003C/em>\u003C/td>\n\u003Ctd>Actionable, traceable engineering proposal with explicit clearance impact\u003C/td>\n\u003Ctd>Verify that \u003Cspan class=\"math-inline\">0.11 mm\u003C/span> spacing and NFP removal meet electrical/impedance rules; approve \u003Ccode>CAM-B1\u003C/code> in writing and update master CAD padstack for future builds\u003C/td>\n\u003C/tr>\n\u003C/tbody>\u003C/table>\n\u003Ch3>What to Include in Your PCB Fabrication RFQ\u003C/h3>\n\u003Cp>To eliminate annular ring holds during CAM engineering, include the following in your \u003Ca href=\"/it/pcb-manufacturing/\">PCB manufacturing\u003C/a> release package:\u003C/p>\n\u003Cul>\n\u003Cli>\u003Cstrong>Synchronized Artwork and Drill Files:\u003C/strong> Gerber (\u003Ccode>RS-274X\u003C/code> / \u003Ccode>Gerber X2\u003C/code>), \u003Ccode>ODB++\u003C/code>, or \u003Ccode>IPC-2581\u003C/code> data with an explicit drill table stating whether nominal drill values represent \u003Cstrong>Finished Hole Size (FHS)\u003C/strong> or \u003Cstrong>uncompensated tool diameters\u003C/strong>.\u003C/li>\n\u003Cli>\u003Cstrong>Governing Acceptance Standard and Class:\u003C/strong> Specify the exact bare-board standard and class on the master drawing (e.g., \u003Cem>IPC-6012 Class 2\u003C/em> or \u003Cem>IPC-6012 Class 3\u003C/em>, plus whether 90° via breakout is permitted or prohibited).\u003C/li>\n\u003Cli>\u003Cstrong>Inner-Layer NFP and Teardrop Policy:\u003C/strong> State clearly in the fabrication notes whether CAM is authorized to remove non-functional internal pads or add teardrops on inner signal layers, and mark any RF/high-speed nets where pad geometry is frozen for impedance control.\u003C/li>\n\u003Cli>\u003Cstrong>Downloadable Review Templates:\u003C/strong> Use \u003Ca href=\"/assets/blogs/pcb-annular-ring-design/layer-margin-example.csv\">layer-margin-example.csv\u003C/a> and \u003Ca href=\"/assets/blogs/pcb-annular-ring-design/change-tradeoffs.csv\">change-tradeoffs.csv\u003C/a> (\u003Ca href=\"/assets/blogs/pcb-annular-ring-design/README.md\">notes\u003C/a>) to document layer-specific pad/tool budgets across critical via families.\u003C/li>\n\u003C/ul>\n\u003Cp>HILPCB manufactures \u003Ca href=\"/it/products/multilayer-pcb/\">multilayer PCBs\u003C/a> up to 64 layers and sequential \u003Ca href=\"/it/products/hdi-pcb/\">HDI PCBs\u003C/a> using optical and X-ray layer-to-layer registration systems holding alignment typically within \u003Cstrong>±15–25 µm\u003C/strong>, mechanical drills down to \u003Cstrong>0.15 mm\u003C/strong>, and laser microvias down to \u003Cstrong>0.05–0.10 mm\u003C/strong>. Upload your Gerber or ODB++ package when you \u003Ca href=\"/it/quote/\">request a quote\u003C/a> so our CAM engineers can verify inner-layer annular ring margins, pad-to-trace clearances, and drill compensation against your target IPC class before production starts.\u003C/p>\n\u003Cdiv data-component=\"BlogQuickQuoteInline\">\u003C/div>\n\n\u003C!-- faq:start -->\n\u003Ch2>Frequently Asked Questions\u003C/h2>\n\u003Ch3>Why is my fabricator's annular ring calculation smaller than what my CAD software shows?\u003C/h3>\n\u003Cp>Most EDA tools calculate annular ring by subtracting the \u003Cstrong>finished hole diameter\u003C/strong> from the pad diameter, whereas fabricator CAM rules subtract the \u003Cstrong>compensated production drill bit diameter\u003C/strong>. Because plated through-holes are drilled \u003Cspan class=\"math-inline\">0.10--0.15 mm\u003C/span> larger than the finished hole to allow for copper plating and surface finish, the actual copper ring remaining around the drill bit is \u003Cspan class=\"math-inline\">0.05--0.075 mm\u003C/span> narrower per side than the nominal finished-hole calculation.\u003C/p>\n\u003Ch3>Does copper plating inside the hole barrel increase the inner-layer annular ring?\u003C/h3>\n\u003Cp>No. On internal layers, the mechanical drill bit punches directly through the etched inner-layer copper foil. Subsequent electroless and electrolytic copper plating deposits copper onto the inner wall of the hole barrel to form the vertical interconnect, but it does not restore horizontal capture-pad width outside the drilled boundary.\u003C/p>\n\u003Ch3>What is the difference between tangency and annular ring breakout?\u003C/h3>\n\u003Cp>Tangency occurs when the outer perimeter of the drilled hole touches the outer edge of the copper pad (\u003Cspan class=\"math-inline\">0 mm\u003C/span> minimum remaining width at one point without extending outside the pad contour). Breakout occurs when the hole extends past the pad edge (\u003Cspan class=\"math-inline\">W\u003Csub>\\min\u003C/sub> < 0\u003C/span>). While IPC-6012 Class 2 typically allows up to 90° of breakout on vias provided trace junctions remain intact, Class 3 generally requires a continuous minimum annular ring with zero breakout.\u003C/p>\n\u003Ch3>When should I add teardrops instead of enlarging the entire via pad?\u003C/h3>\n\u003Cp>Use teardrops when routing density (such as under a \u003Cspan class=\"math-inline\">0.8 mm\u003C/span> or \u003Cspan class=\"math-inline\">0.65 mm\u003C/span> pitch BGA) prevents enlarging the circular pad diameter without violating trace-to-pad clearance rules. Teardrops reinforce the copper specifically along the trace-entry vector—preventing drill offset from severing the trace-to-pad neck—while keeping the perpendicular sides of the pad within the channel clearance budget.\u003C/p>\n\u003C!-- faq:end -->\n\u003Csection class=\"related-links\" aria-label=\"Link correlati\">\u003Ch3 id=\"related-links\">Link correlati\u003C/h3>\u003Cul>\u003Cli>\u003Ca href=\"/it/blog/what-is-dfm-design-for-manufacturing/\">Cos'è il DFM? Principi di Design for Manufacturing per PCB\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pcb-annular-ring-design/layer-margin-example.csv\">layer-margin-example.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/assets/blogs/pcb-annular-ring-design/change-tradeoffs.csv\">change-tradeoffs.csv\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/it/blog/pcb-finished-hole-size-drill-tolerance/\">Finished Hole Size vs Drill Size: Writing Clear PCB Hole Requirements\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/it/blog/ipc-class-1-2-3/\">IPC Classe 1 vs Classe 2 vs Classe 3: Criteri di fabbricazione, microsezioni e impatto sui costi BOM\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/it/blog/via-filling-material-guide-pcb-stackup-materials/\">Guida ai materiali di riempimento delle vie per gli stack-up PCB\u003C/a>\u003C/li>\u003Cli>\u003Ca href=\"/it/pcb-manufacturing/\">PCB manufacturing\u003C/a>\u003C/li>\u003C/ul>\u003C/section>",[14,18,21,24],{"question":15,"answer":16,"answerText":17},"Why is my fabricator's annular ring calculation smaller than what my CAD software shows?","Most EDA tools calculate annular ring by subtracting the **finished hole diameter** from the pad diameter, whereas fabricator CAM rules subtract the **compensated production drill bit diameter**. Because plated through-holes are drilled $0.10\\text{--}0.15\\text{ mm}$ larger than the finished hole to allow for copper plating and surface finish, the actual copper ring remaining around the drill bit is $0.05\\text{--}0.075\\text{ mm}$ narrower per side than the nominal finished-hole calculation.","Most EDA tools calculate annular ring by subtracting the finished hole diameter from the pad diameter, whereas fabricator CAM rules subtract the compensated production drill bit diameter. Because plated through-holes are drilled $0.10\\text{--}0.15\\text{ mm}$ larger than the finished hole to allow for copper plating and surface finish, the actual copper ring remaining around the drill bit is $0.05\\text{--}0.075\\text{ mm}$ narrower per side than the nominal finished-hole calculation.",{"question":19,"answer":20,"answerText":20},"Does copper plating inside the hole barrel increase the inner-layer annular ring?","No. On internal layers, the mechanical drill bit punches directly through the etched inner-layer copper foil. Subsequent electroless and electrolytic copper plating deposits copper onto the inner wall of the hole barrel to form the vertical interconnect, but it does not restore horizontal capture-pad width outside the drilled boundary.",{"question":22,"answer":23,"answerText":23},"What is the difference between tangency and annular ring breakout?","Tangency occurs when the outer perimeter of the drilled hole touches the outer edge of the copper pad ($0\\text{ mm}$ minimum remaining width at one point without extending outside the pad contour). Breakout occurs when the hole extends past the pad edge ($W_{\\min} \u003C 0$). While IPC-6012 Class 2 typically allows up to 90° of breakout on vias provided trace junctions remain intact, Class 3 generally requires a continuous minimum annular ring with zero breakout.",{"question":25,"answer":26,"answerText":26},"When should I add teardrops instead of enlarging the entire via pad?","Use teardrops when routing density (such as under a $0.8\\text{ mm}$ or $0.65\\text{ mm}$ pitch BGA) prevents enlarging the circular pad diameter without violating trace-to-pad clearance rules. Teardrops reinforce the copper specifically along the trace-entry vector—preventing drill offset from severing the trace-to-pad neck—while keeping the perpendicular sides of the pad within the channel clearance budget.",[28,29,30,31],"annular ring","PCB pad size","annular ring breakout","PCB DFM","pcb-annular-ring-design","en",[33,35,36,37,38],"de","cn","fr","ru",{"blog":40,"breadcrumb":49},{"@context":41,"@type":42,"headline":4,"description":5,"image":8,"url":43,"datePublished":6,"dateModified":6,"timeRequired":11,"keywords":44,"articleSection":7,"author":45,"publisher":48},"https://schema.org","BlogPosting","https://hilpcb.com/it/blog/pcb-annular-ring-design/","annular ring, PCB pad size, annular ring breakout, PCB DFM",{"@type":46,"name":47},"Organization","HILPCB",{"@type":46,"name":47},{"@context":41,"@type":50,"itemListElement":51},"BreadcrumbList",[52,57,61],{"@type":53,"position":54,"name":55,"item":56},"ListItem",1,"Home","https://hilpcb.com/",{"@type":53,"position":58,"name":59,"item":60},2,"Blog","https://hilpcb.com/it/blog/",{"@type":53,"position":62,"name":32,"item":43},3,1793497495788]