Phase delay—the time a signal takes to travel through a PCB trace—becomes a critical design parameter at high frequencies and data rates. When signals must arrive simultaneously, maintain specific timing relationships, or preserve phase coherence across frequency, understanding and controlling propagation delay is essential.
This guide covers phase delay fundamentals and practical techniques for managing timing in high frequency PCB signal integrity applications.
HILPCB manufactures high frequency PCBs with controlled dielectric thickness (±5%) for consistent propagation delay, supporting differential pair skew requirements down to ±5 ps.
In This Guide
- Understanding Phase Delay
- Calculating Propagation Delay
- Differential Pair Skew
- Multi-Lane Timing Requirements
- Length Matching Techniques
- Manufacturing Factors Affecting Delay
- Design Guidelines and Best Practices
Understanding Phase Delay
Signals don't travel instantaneously through PCB traces—they propagate at a finite velocity determined by the surrounding dielectric material. This propagation delay has several important consequences for high-frequency design.
Propagation Velocity
Electromagnetic signals in vacuum travel at the speed of light (c ≈ 3×10⁸ m/s or about 12 inches per nanosecond). In PCB materials, signals travel slower by a factor related to the dielectric constant:
Velocity = c / √Dk (approximately, for stripline)
For FR-4 with Dk ≈ 4.3, signals travel at roughly half the speed of light—about 6 inches per nanosecond.
Phase Delay vs. Group Delay
Phase delay is the time for a single frequency component to travel through the structure. Group delay is the rate of change of phase with frequency—representing how a modulated signal's envelope propagates.
In ideal (non-dispersive) transmission lines, phase and group delay are equal. In real PCBs with frequency-dependent dielectric constant, they differ slightly—causing signal distortion.
Why Phase Delay Matters
Phase delay becomes critical when:
- Differential pairs must maintain balance (skew)
- Multiple lanes must arrive simultaneously (bus timing)
- Phase relationships must be preserved (RF systems)
- Clock and data must align (source-synchronous interfaces)
Calculating Propagation Delay
Accurate delay estimation enables proper timing analysis and length matching requirements.
Basic Delay Formulas
Stripline (trace between two planes): Delay ≈ 85 ps/inch × √Dk
Microstrip (trace on outer layer): Delay ≈ 85 ps/inch × √(0.475×Dk + 0.67)
The microstrip formula accounts for the field partially in air (Dk=1) and partially in the substrate.
Example Calculations
For FR-4 (Dk ≈ 4.3):
- Stripline: 85 × √4.3 ≈ 176 ps/inch
- Microstrip: 85 × √(0.475×4.3 + 0.67) ≈ 140 ps/inch
For Rogers RO4350B (Dk ≈ 3.48):
- Stripline: 85 × √3.48 ≈ 159 ps/inch
- Microstrip: 85 × √(0.475×3.48 + 0.67) ≈ 128 ps/inch
Factors Affecting Delay
Dielectric constant (Dk): Higher Dk = slower propagation. Dk varies with:
- Material type (FR-4 vs. PTFE vs. ceramic)
- Frequency (Dk typically decreases at higher frequencies)
- Temperature (usually small effect)
- Resin content in prepreg (affects composite Dk)
Trace structure: Microstrip is faster than stripline in the same material because part of the field travels in air.
Copper roughness: Minor effect, but roughness can slightly increase effective path length.
Propagation Delay by Material
Differential Pair Skew
Differential signaling transmits data as the voltage difference between two complementary traces. For proper operation, both traces must have equal delay—any mismatch is called "skew."
What Causes Skew
Length mismatch: The most obvious cause. If one trace is longer, it has more delay.
Different reference distances: If P and N traces have different distances to the reference plane, they have different effective Dk and thus different velocities.
Asymmetric routing: Different bend radii, via placements, or layer transitions between P and N.
Fiber weave effect: In woven glass fabric, traces aligned with glass bundles see different Dk than traces over resin-rich areas. Adjacent traces may experience different Dk.
Skew Effects
Skew converts differential signals partially into common-mode, degrading performance:
- Reduced differential swing
- Increased EMI (common-mode radiates more)
- Degraded receiver common-mode rejection
- Timing uncertainty at receiver
Skew Requirements by Interface
| Interface | Typical Max Skew |
|---|---|
| USB 2.0 | < 100 ps |
| USB 3.x | < 15 ps |
| PCIe Gen 3 | < 5 ps |
| PCIe Gen 4/5 | < 3 ps |
| HDMI 2.1 | < 10 ps |
| 100G Ethernet | < 5 ps |
At 140 ps/inch, 5 ps skew corresponds to roughly 0.9 mils length difference—extremely tight tolerances requiring careful design and manufacturing.
Multi-Lane Timing Requirements
Modern high-speed interfaces use multiple parallel lanes (PCIe x16, DDR data bus, USB4). These lanes must maintain timing alignment within the receiver's sampling window.
Intra-Pair Matching (Within Differential Pair)
The P and N traces of a single differential pair must be matched to skew specifications discussed above. This is the tightest requirement.
Inter-Pair Matching (Between Lanes)
Different lanes must arrive within a timing window—typically related to the unit interval (UI):
- PCIe: ±0.05 UI typical
- DDR: specific setup/hold times relative to strobe
Inter-pair matching is usually less stringent than intra-pair but still requires attention.
Byte Lane Matching
Memory interfaces often group 8 data bits with a strobe signal. All signals in a byte lane must be matched to the strobe timing.
Example (DDR4): Data-to-strobe skew requirement ~50-100 ps
Clock Distribution
Source-synchronous interfaces transmit clock with data. Clock routing requires:
- Matched delay to all receivers
- Minimal skew between clock edges
- Appropriate delay relative to data (setup/hold)
Length Matching Techniques
Physical length matching compensates for delay differences, ensuring signals arrive simultaneously.
Serpentine (Accordion) Routing
The most common technique: add meandering sections to shorter traces to equalize length.
Guidelines:
- Serpentine amplitude: 3× trace width minimum
- Segment spacing: 3× trace width minimum (larger is better)
- Keep serpentine compact, away from pair mate
- Place close to length mismatch source
Caution: Excessive serpentine can cause self-coupling issues. For very high frequencies, serpentine segments may radiate.
Trombone Routing
Extends trace length using rounded bends rather than tight serpentine. Lower coupling issues but uses more space.
Via Matching
Each via adds delay (~20-30 ps typical). Match via counts between paired traces, or compensate with length adjustment.
Layer Transition Matching
If traces change layers at different points, accumulated delay differs. Match layer transition locations when possible.
Component Placement
Strategic component placement minimizes required length matching. Place differential pair endpoints at equal distances; align multi-lane endpoints.
Length Matching Conversion
Manufacturing Factors Affecting Delay
Design specifies nominal delay; manufacturing introduces variations.
Dielectric Thickness Variation
Dielectric thickness affects effective Dk seen by traces. Laminate thickness tolerances of ±10% can shift delay by similar amounts.
Mitigation: Specify tighter dielectric tolerance for critical layers; HILPCB offers ±5% dielectric control.
Dk Variation
Even within a single material lot, Dk varies:
- Across panel position
- Between batches
- With resin content in prepreg
Mitigation: Use materials with tighter Dk tolerance; specify delay-critical requirements to manufacturer.
Fiber Weave Effect
Glass fabric in FR-4 and similar materials has a woven structure with glass bundles and resin-rich channels. Traces aligned with glass see higher effective Dk than those over resin.
Mitigation:
- Rotate traces relative to weave (20° or 45°)
- Use spread glass or alternative weave patterns
- Specify weave-mitigated materials for critical applications
Registration and Layer Alignment
Misregistration between layers can shift trace positions relative to reference planes, affecting impedance and delay.
HILPCB capability: ±15-25 μm layer registration
Design Guidelines and Best Practices
Practical recommendations for managing phase delay in HF designs.
During Schematic Design
- Identify delay-critical nets early
- Group related signals (differential pairs, byte lanes)
- Consider component pin assignments for routing efficiency
During Layout
- Place matched components at equal distances
- Route differential pairs together, not separately
- Match layer transitions between paired signals
- Apply serpentine at bends and length mismatches, not at trace ends
- Verify length matching with design rule checks
Stackup Considerations
- Use consistent dielectric material on delay-critical layers
- Consider asymmetric dielectric effects on microstrip
- Specify dielectric tolerance for matched delay applications
Documentation
- Communicate delay requirements to manufacturer
- Specify absolute delay when needed (not just length)
- Indicate skew requirements on critical nets
- Note any special material requirements (weave, Dk tolerance)
Verification
- Simulate timing before manufacturing
- Measure TDR on test coupons
- Verify eye diagrams meet specifications
HILPCB Phase Delay Capabilities
HILPCB manufactures high frequency PCBs with controlled delay characteristics:
Dielectric Control: ±5% thickness tolerance on specified layers for consistent propagation delay.
Registration: ±15-25 μm layer alignment for symmetric differential pairs.
Materials: Full range of Dk-stable materials including low-Dk options for faster propagation.
Skew Verification: Differential delay matching verified through TDR testing with ±5 ps measurement capability.
Fiber Weave Options: Spread glass and alternative weave materials available for critical applications.
From prototype through volume production, HILPCB delivers consistent delay characteristics for timing-critical applications.
Contact HILPCB for high frequency PCB design review and manufacturing quotation.