PCB Via Inductance Calculator

Estimate via inductance, inspect reactance at your frequency, and compare practical geometry changes. Includes a frequency sweep and a clear explanation of what the model excludes.

Method & assumptions ↓

01 · Define your via

mm
mm

Use the conductive span between connected layers. Diameter means the conductive barrel, not the pad or antipad. For a finished hole, add twice the radial plating thickness.

MHz

Use signal frequency, not data rate. An ideal inductor has reactance X = 2πfL.

Use a decimal point (.) without thousands separators.

Get a PCB quote →

02 · Understand the result

Calculate to see your estimate, frequency curve and geometry comparison.

Via geometry

Conductive barrel and connected span

Conductive barrel and connected spanSchematic only; plating is exaggerated. h spans the connected layers, and d spans the conductive barrel.hd

Calculate to show dimensions.

Schematic only; plating is exaggerated. h spans the connected layers, and d spans the conductive barrel.

Return path matters

Conceptual return path — not a field solution

Conceptual return path — not a field solutionA nearby return connection can reduce loop area. Its effect is not included in this single-via estimate.
Signal viaReturn viaReference connection
A nearby return connection can reduce loop area. Its effect is not included in this single-via estimate.

METHOD & SOURCES

How the estimate works

With h and d in millimetres, L in nH is 0.2 × h × [ln(4h/d) + 1]. This is the via approximation published in TI SLLA284G, Equation 2, page 16. ln is the natural logarithm.

L [nH] = 0.2 × h [mm] × [ln(4h/d) + 1]
X [Ω] = 2π × f [Hz] × L [H]

The diameter is a geometric approximation to the conductive barrel. Pad size, antipad clearance, plating distribution and nearby copper are not separate inputs to this model.

This tool accepts 0.01–100 mm geometry and screens out h < d. These are conservative application limits for this calculator, not manufacturing capabilities or a validated accuracy range.

Inductive reactance is X = 2πfL, with frequency in Hz and inductance in H. At DC, ideal reactance is zero; real resistance remains outside this calculation.

The optional rise-time mode uses f = 0.35/tr for a single-pole 10–90% bandwidth estimate. Other edge shapes use other conventions. Enter a known frequency whenever it is available.

A real transition depends on its return path and surrounding planes. Mutual inductance, parallel vias, capacitance, resonance and frequency-dependent losses require a more complete model.

Worked example: length, diameter and return paths →

Published by HilPCB · Method reviewed November 8, 2026

COMMON QUESTIONS

PCB via inductance questions

Is this the signal-loop inductance?

No. This is an isolated-via geometry estimate. The actual loop includes the return path; nearby return vias and plane continuity can materially change it.

Should I use board thickness or via length?

Use the conductive span between the layers being connected. It can equal board thickness for a through connection; a blind connection can be shorter.

Why does rise-time mode differ from other calculators?

A rise time does not define one unique frequency. This tool states the 0.35/tr single-pole bandwidth convention; some tools use 0.5/tr. At the same actual frequency and geometry, X = 2πfL is unchanged.

Does twice the via count halve inductance?

Not generally. Mutual coupling and shared return paths affect the array. This tool does not apply a 1/N inductance rule.

Can I use this above 10 GHz?

The frequency control is limited to 10 GHz. Even below that limit, the fixed-L model may miss capacitance and resonance; use a field solver or measured data for high-frequency verification.