PCB Via Capacitance Calculator
Estimate via parasitic capacitance, inspect capacitive reactance at your frequency, and explore pad, antipad and total PCB thickness sensitivity.
Method & assumptions ↓02 · Understand the result
Calculate to see your estimate, frequency curve and geometry comparison.
Via geometry · Top view
Calculate to show dimensions.
Cross section
Calculate to show dimensions.
METHOD & SOURCES
How the estimate works
TI SLLA284G, Equation 1, page 15 estimates through-via capacitance using total PCB thickness T, pad diameter D1, antipad diameter D2 and relative permittivity εr.
C [pF] = (1.41/25.4) × εr × T [mm] × D1 / (D2 − D1)
|Xc| [Ω] = 1 / (2π × f [Hz] × C [F])
The source equation uses inches. Dividing its coefficient by 25.4 gives this millimetre form; D1 and D2 must use the same units. T is the total PCB thickness, not the nearest reference-plane spacing.
This is a through-via geometry approximation, not a parallel-plate model, a blind-via model, a sum over planes or a field solution. Plane count, hole diameter and conductive barrel diameter are not additional inputs.
Accepted geometry is 0.01–100 mm, with D2 greater than D1; relative permittivity is 1–30. These are application screens, not manufacturing capabilities or validated accuracy limits.
Frequency accepts DC (0) or 0.000001–10000 MHz. Capacitance stays fixed as frequency changes; ideal capacitive reactance magnitude is 1/(2πfC). At DC, the ideal capacitor is an open circuit.
Small pad-to-antipad gaps make the formula especially sensitive to dimensional tolerances. The geometry alternatives illustrate sensitivity only; they do not establish manufacturability.
Losses, coupling, inductance and resonance are not calculated. The fixed-C curve does not predict insertion loss, usable bandwidth or the behavior of a complete via transition.
Worked example: pad and antipad capacitance →
Published by HilPCB · Method reviewed November 8, 2026
COMMON QUESTIONS
PCB via capacitance questions
Does frequency change the capacitance?
No. Geometry and relative permittivity set the capacitance in this approximation. Frequency changes the ideal reactance magnitude, which falls as frequency increases. Real dielectric properties can vary with frequency.
Is T the spacing to the nearest reference plane?
No. T is total PCB thickness in the TI through-via approximation. Substituting a nearby plane spacing changes the meaning of the equation.
What do D1 and D2 mean?
D1 is the via pad diameter. D2 is the clearance or antipad diameter in the reference planes. The hole and conductive barrel diameter are not separate model inputs.
Can I use this for blind vias or add plane capacitances?
This tool implements the published through-via approximation. It does not model blind vias or sum individual plane contributions. Use a model matched to the actual stackup for those cases.
Are the alternative geometries manufacturing recommendations?
No. The alternatives show sensitivity to one changed dimension at a time. Check annular rings, drill tolerances, clearances and stackup requirements with your fabricator.
What does open circuit at DC mean?
An ideal capacitor passes no steady DC current. The calculator shows Open circuit instead of a finite reactance. Real leakage and dielectric losses are not calculated.