PCB Via Current Calculator
Estimate via current from finished hole size and barrel plating. Compare two empirical scenarios, inspect the copper cross-section, and calculate losses at your selected load.
Equivalent-conductor method & limitations ↓Compare via scenarios
Exact copper annulus · heuristic thermal comparison
I = k × ΔT^0.44 × A^0.725, with A in mil². The trace-derived coefficients below are not validated IPC via thermal limits.
Enter the barrel geometry and select Calculate to compare both scenarios and selected-load losses.
Copper annulus · top view
Through via
Blind via
Buried via
Calculate to show actual dimensions.
Blind vias reach one surface; buried vias remain fully internal. L is the connected span for the via being evaluated.
Heuristic comparison only. Coupled heating and unequal current sharing are excluded; these values are not certified via limits.
METHOD & SOURCES
How the via estimate works
A plated via is a hollow copper barrel. This tool applies a trace-current relationship to its exact annular copper area. This adaptation is a planning heuristic, not a validated via thermal model or an IPC-certified limit.
A = π × t × (D + t)
I = k × ΔT0.44 × A0.725
D is the finished internal hole diameter and t is radial barrel plating, in the same length unit. The outer barrel diameter is D + 2t. Convert the copper area to mil² before applying the current equation; ΔT is temperature rise in °C.
The through-via scenario uses k = 0.048 and the blind/buried scenario uses k = 0.024, borrowed from external and internal trace coefficients. These labels do not model actual via cooling. A blind via reaches one board surface; a buried via lies entirely between internal layers.
Resistance is R = ρ(T)L/A, with copper resistivity 1.724 × 10⁻⁸ Ω·m at 20 °C and coefficient 0.00393/°C. T is ambient plus the selected rise, not a solved operating temperature. For N identical vias sharing equally, array resistance is R/N, voltage drop is Iload × R/N and total power is Iload² × R/N.
Losses use your selected total load current. They are not calculated at the displayed capacity estimates. N times the single-via current is an ideal comparison only: unequal routing resistance and coupled heating can reduce real array performance.
Length changes resistance and losses but does not enter the empirical current equation. Pad and plane geometry, laminate, airflow, via spacing, current crowding, transient current and mutual heating are outside this model. Verify the actual board and choose engineering margin.
Calculator limits: hole 0.01–10 mm; plating 0.1–500 µm; barrel length 0.001–100 mm; ambient −40 to 125 °C; rise above zero to 100 °C; combined temperature at most 150 °C; load 0–1,000,000 A; 1–10,000 vias. These are input limits, not manufacturing capabilities or validated thermal ranges.
- Texas Instruments TIDUCS7, page 9, Equation 7: the underlying trace-current relationship
- IPC-2152 contents: thermal topics beyond this simplified model
- Copper Development Association: copper electrical properties
Worked example: barrel resistance and parallel vias →
Published by HilPCB · Method reviewed November 8, 2026
COMMON QUESTIONS
PCB via current questions
Check the geometry and assumptions before choosing your vias.
Should I enter drill diameter or finished hole diameter?
Enter the finished internal hole diameter after plating. Enter barrel plating separately as a radial thickness. Drill diameter, finished hole size and pad diameter are different dimensions.
Does doubling the via count double usable current?
Only under ideal equal-sharing assumptions. Real vias may have different path resistances and heat each other. Treat the array estimate as a comparison and verify the current distribution and thermal design.
Why is the blind/buried estimate half the through estimate?
The two borrowed trace coefficients differ by a factor of two. This is a model assumption, not a measured universal relationship between via types. The same geometry has the same calculated barrel resistance in either scenario.
Can this replace a thermal simulation or a safe-current specification?
No. It gives a starting estimate for an equivalent conductor. Use the finished plating specification, real stackup and operating conditions for engineering verification.