High-speed PCB behavior depends on edge rate, electrical length and the interconnect, not a universal 100 MHz or 10 Gbps boundary. Review the complete channel—packages, traces, vias, connectors and any cables—against the selected interface and device requirements before choosing laminate or routing rules.
HILPCB’s design support includes SI/PI and thermal analysis, while its high-speed PCB and multilayer routes provide manufacturing inputs for the released construction. Modeling, coupon acceptance and system qualification remain distinct deliverables.
When does a PCB become high-speed, and how do you budget channel loss?
Compare one-way propagation delay with the actual signal transition time. A useful screening ratio is trace length × delay per length / edge time; the acceptable ratio depends on the interface and the error tolerated. No single length threshold proves that reflections are negligible or mandates one termination.
For an assumed example, a 50 ps edge and 165 ps/in propagation delay give 50 / (2 × 165) ≈ 0.15 in, or 3.8 mm. That is the result of the chosen half-edge-time heuristic, not a universal failure boundary. Use the selected stackup and transmitter/receiver models for validation.
Allocate loss using consistent reference planes. As bookkeeping, the PCB allocation is the full-channel allowance minus the package, connector and other allocated losses and the chosen margin. Cascading actual S-parameters also needs mismatch, reflection and coupling effects; a scalar sum is not a full channel simulation.
| Interface example | Nominal operating rate | Signaling / Nyquist relationship | Budget and model to obtain |
|---|---|---|---|
| DDR4-3200 | 3.2 Gb/s per data pin | NRZ; nominal 1.6 GHz Nyquist | Device/topology, timing and channel requirements |
| DDR5-6400 | 6.4 Gb/s per data pin | NRZ; nominal 3.2 GHz Nyquist | Actual topology, package and controller guidance |
| PCIe 4.0 | 16 GT/s | NRZ; 8 GHz Nyquist | Applicable Base/CEM and platform allocation |
| PCIe 5.0 | 32 GT/s | NRZ; 16 GHz Nyquist | Defined reference planes and package/connector allocation |
| PCIe 6.0 | 64 GT/s data-rate designation | PAM4 at 32 GBd; 16 GHz Nyquist | Applicable revision, channel topology and validation method |
| 56G PAM4 illustration | 56 Gb/s before overhead assumptions | 28 GBd; 14 GHz Nyquist | Actual PHY rate, coding and channel class |
| 112G PAM4 illustration | 112 Gb/s before overhead assumptions | 56 GBd; 28 GHz Nyquist | Actual PHY rate, coding and channel class |
Nyquist is a comparison frequency, not the highest frequency needed in every model. The PCI-SIG PAM4 explanation supports the PCIe 6.0 relationship; the AI-server channel review shows why published total loss cannot all be assigned to board traces. Conductor and dielectric loss contributions depend on geometry, foil, material and band; neither always dominates above 10 GHz.
Stackup architecture: balancing dielectric loss against copper foil roughness
Select laminate and foil against the channel model, assembly exposure and a construction the fabricator can build. Loss-class labels are not interchangeable specifications, and a family name does not establish attenuation per inch or price.
For copper with assumed conductivity σ = 5.8 × 10^7 S/m and permeability μ ≈ μ0, skin depth is:
δ = 1 / √(π f μ σ) ≈ 66,000 / √(f in Hz) µm.
At 28 GHz this gives about 0.39 µm. Equivalently, the coefficient is about 66 when frequency is in MHz. This ideal material calculation is not a finished-trace loss model. Roughness can alter conductor loss; specify the profile metric and model rather than equating Rq and Rz or promising a fixed percentage improvement.
| Material or construction option | Data to compare | Manufacturing question | Evidence before selection |
|---|---|---|---|
| General FR-4 grade | Actual Dk/Df by frequency/method, temperature properties | Is the proposed length and foil adequate? | Channel result using the offered construction |
| Isola FR408HR example | Manufacturer’s grade/construction data | Which core/prepreg and foil are offered? | Model input tied to the actual grade and sheet |
| Panasonic Megtron example | Exact product suffix and available foil | Is the chosen construction available and qualified? | Datasheet, proposed stackup and loss correlation |
| Other low-loss resin systems | Comparable measurement conditions | What processing and bonding route is required? | Exact grade, construction and process review |
| Rogers RO4350B example | Process Dk 3.48 and Df 0.0037 at 10 GHz/23°C; design Dk is a different value | Does this hydrocarbon/ceramic construction fit the circuit? | Manufacturer’s RO4000 sheet and relevant model |
| Hybrid stackup | Layer-specific materials, foil and pressed geometry | Are bonding, registration and thermal behavior compatible? | Approved combined construction and substitution rules |
Select the laminate using the modeled and measured channel margin at the intended length. Compare the complete channel and manufacturing variation, then use the low-loss PCB and high-Tg FR-4 discussions for electrical and thermal selection boundaries.
Controlled impedance: closing the gap between ±10% and ±5% tolerances
Set impedance and tolerance from the interface, transmitter/receiver and selected topology. Values such as 50 Ω single-ended or 85/90/100 Ω differential are examples, not interchangeable targets for every net.
Etched and plated traces need the finished copper geometry, dielectric and foil model used by the solver. The sidewall shape and artwork compensation are process-specific; do not assume one angle, width reduction or resulting impedance error for every 1 oz trace.
| Control | What changes the result | What to agree before routing | Evidence for release |
|---|---|---|---|
| Copper and geometry | Foil, plating, width/spacing and section shape | Offered finished dimensions and tolerances | Process data and relevant dimensional checks |
| Dielectric | Pressed thickness, resin/glass construction and Dk model | Approved stackup and permitted changes | Stackup confirmation and agreed sections |
| CAM compensation | Actual etch process and copper construction | Design-owner approval of changed geometry | Released artwork and solver correlation |
| Coupons | Location, representation, method and sampling | Target, tolerance, measurement window and decision rule | Identified TDR records with stated scope |
HILPCB publishes reviewed ±5% impedance routes for eligible constructions. Confirm the particular stackup, target and coupon plan; neither ±5% nor ±10% implies one mandatory laminate class, equipment recipe, sampling scheme or fixed price premium. Use the impedance calculator for initial geometry and obtain fabrication review before release.
Critical routing constraints: via stub backdrilling, ground returns, and fiber weave skew
Signal degradation on dense digital boards frequently originates not from the uniform trace, but from discontinuities where signals transition between layers.
1. Via stub resonance and depth-controlled backdrilling
When an inner-layer trace connects through a through-hole via, the unused portion of the barrel hanging beyond the destination layer acts as an open-circuit transmission line stub. An ideal open stub can create a quarter-wave resonance; the estimate below is a screening model for a uniform unloaded structure:
As an ideal open-stub example, assume an electrical length of 1.9 mm and effective relative permittivity 3.5. The quarter-wave estimate is c / (4 × 0.0019 × √3.5) ≈ 21.1 GHz. This is not a measured via resonance: pads, coupling, return paths and dispersion change the transition, and a notch estimate alone does not prove a link failure.
Choose backdrilling only where the transition model and channel requirements justify it. State connected layers, drill side/diameter, must-not-cut clearance, residual-stub limit and tolerances on the drawing. Confirm the worst-case stackup and inspection route with the fabricator. A 20 Gbps rate alone does not mandate backdrilling or one universal residual length.
2. Return path continuity and ground stitching vias
For fast signal components, review the adjacent reference and return transition along with the trace. Avoid routing across a gap in the intended reference.
- Same ground net: Nearby ground return vias can connect reference planes across a signal-layer transition; location follows the geometry and interface requirement.
- Different reference nets: Prefer a consistent reference where practical. Any coupling network needs electrical analysis and must respect the design’s isolation requirements and intended DC connections; a universal 0.1 µF capacitor is not a safe substitute for that review.
- Slots and via fields: Inspect the actual return copper, including dense antipads and connector escapes, rather than treating a plane name as proof of continuity.
TI’s SLLA414A layout guidance discusses return paths and via-stub mitigation for specified interfaces; use the relevant device guidance rather than transferring its dimensions to every board.
3. Glass weave skew and fiber bundle routing
Glass/resin distribution can change the effective delay under the two members of a pair. For an assumed uniform section, propagation scales approximately with length × √εeff / c; local weave behavior needs an appropriate effective model rather than pure glass/resin Dk substituted as if the whole trace saw either material.
Discuss spread-glass constructions, route angle and material options with the fabricator and SI owner. Glass style numbers alone do not guarantee a spread construction, and route angle or skew limits must follow the actual channel. Verify pair skew, layer differences and the actual channel with the offered material.
How to troubleshoot VNA and TDR signal-integrity failures on prototypes
Compare measurements with the released design, calibration and specimen before assigning a cause.
| Failure signature | Competing causes to investigate | Useful evidence | Candidate action and acceptance |
|---|---|---|---|
| Narrow S21 notch | Via/connector resonance or fixture effects | Calibrated reference planes, transition model and physical geometry | Correct the identified feature; confirm the actual channel limit |
| Excessive pair skew | Weave, unequal layers/geometry, package or launch | Consistent delay model and measurements | Review construction/routing against the interface budget |
| TDR step | Width, dielectric, reference or launch discontinuity | Profile/window, exported geometry and relevant section | Reconcile the measured structure with its target and tolerance |
| Excessive insertion loss | Dielectric, foil, geometry or fixture model | Material/foil identity, calibrated loss data and de-embedding | Change the relevant construction and revalidate the channel |
| Intermittent microvia connection | Interface integrity, thermal history or geometry | Electrical monitoring, agreed stress and failure analysis | Qualify the revised via/process; no universal stacked-via ban or wrap value follows |
| Crosstalk | Coupled length, spacing, reference paths or launches | Correct port mapping, aggressor conditions and channel model | Use geometry-specific isolation limits rather than a universal 3W/4W rule |
Procurement and supply chain cost drivers for high-speed boards
Compare the actual material, processing and evidence package rather than generic percentage adders.
| Cost or schedule driver | What to confirm | Sourcing/quality decision |
|---|---|---|
| Low-loss core and prepreg | Exact grade, glass, foil, inventory and shelf life | Approved construction, alternatives and quoted availability |
| Backdrilling | Number of operations, tolerances, clearance and inspection | Channel-justified features and agreed residual-stub evidence |
| Impedance control | Geometry, tolerance, coupon location and sampling | Required records and acceptance decision rule |
| Foil choice | Profile/model and bonding compatibility | Channel benefit versus availability and process qualification |
| Sequential lamination/HDI | Via spans, cycles, handling and reliability evidence | Qualified combined route and quoted lead time |
Before ordering, confirm coupon sampling, backdrill inspection, actual foil construction and hybrid-material compatibility. Compare foil data, coupon sampling and process time within the supplier’s actual offer.
Submit / Release Aid
Send with the RFQ or release package:
- Native
ODB++orIPC-2581archive (orGerber X2with netlist) plus Excellon drill and backdrill files. - Master stackup drawing specifying target laminate slash sheet / grade, glass weave style (
1067,1078,2116,3313), copper weight, and foil profile (VLPorHVLP). - Controlled-impedance table listing single-ended and differential target impedances (
50 Ω,85 Ω,90 Ω,100 Ω), tolerance (±10%or±5%), trace widths/spacings, and reference layers. - Backdrill schedule table defining start layer, must-not-cut layer, and maximum allowable residual stub length derived from the actual transition model and fabrication tolerances.
Request from the supplier (evidence you need before sign-off):
- Factory-modeled press stackup sheet showing actual core/prepreg constructions, effective Dk/Df at your Nyquist frequency, and CAM-compensated trace widths.
- TDR impedance coupon test report (and VNA S21/S11 insertion-loss sweep where specified) tied to each production panel.
- Metallographic cross-section report verifying dielectric layer thickness, trapezoidal etch geometry, and residual backdrill stub length.
- Raw laminate Certificate of Conformance (CoC) confirming lot traceability for all low-loss cores and prepregs.
Owner for each step:
- Designer: Channel loss budget simulation, differential pair routing, return-path stitching vias, and backdrill net assignment.
- Quality: Coupon TDR and microsection acceptance criteria, solder-float thermal stress sign-off, and lot traceability review.
- Procurement: Low-loss laminate stock and lead-time verification, hybrid stackup cost comparison, and test-scope confirmation at quotation.
Gate for verification (release decision by stage):
- EVT: Factory stackup simulation sign-off + first-article TDR coupon and backdrill cross-section check.
- DVT: Full-channel eye diagram / VNA S-parameter validation across temperature extremes.
- PVT: Multi-panel TDR Cp/Cpk distribution check across the pilot production lot.
- MP: Lot-by-lot TDR coupon logging and raw laminate CoC verification prior to shipment.
When your stackup architecture and impedance targets are ready for manufacturing review, explore our high-speed PCB, multilayer PCB, and PCB design services, or submit your design files to request a quote.
When does a PCB trace require controlled-impedance routing?
Use the actual edge rate, propagation delay, interface and allowed reflection/timing error to assess electrical length. Then define the required impedance, reference path and termination using the device/channel model; there is no universal half-inch or one-tenth-rise-time acceptance rule.
Why is copper foil roughness critical above 10 GHz?
Roughness can affect conductor loss when its scale is relevant to current distribution. For assumed copper properties, skin depth is about 0.39 µm at 28 GHz. Compare the actual foil metric/model and channel measurements; no fixed roughness-loss percentage applies to every geometry.
How short must backdrill stubs be for 25 Gbps channels?
Derive the residual-stub limit from the complete via/connector channel model and the actual rate, modulation and reference planes. Specify worst-case length and drill tolerance with must-not-cut clearance, then inspect the agreed structure. Confirm that the resulting channel meets its specified performance and inspection limits.
How do ±10% and ±5% impedance tolerances compare in production cost?
A tighter tolerance can require a different construction, process window and verification plan. Confirm the actual supplier capability and quote, including coupon sampling and reports; no universal percentage premium or compulsory equipment recipe follows from ±5%.