A PCB solderability test answers whether the specified board surfaces will wet with solder under controlled conditions. Before releasing a stored lot or qualifying a new finish, identify the surfaces to be tested, the assembly process, and the acceptance method. A passing coupon supports that decision; it does not establish the fatigue life of the finished solder joints.
For finish selection before fabrication, use the PCB surface finish comparison. The decision here is narrower: which solderability evidence is needed before those boards and their components enter assembly?
Which solderability test method fits the item being purchased?
Bare-board testing and electronic component solderability testing address opposite sides of a future joint. A good result on the board does not qualify the component termination, and vice versa.
| Item or question | Test basis to identify in the order | Evidence to request | What it does not establish |
|---|---|---|---|
| Bare PCB lands, pads and plated-through holes | J-STD-003, specified revision and applicable method | Results for the defined board features or representative coupons, finish and conditioning | Component termination condition or assembled-joint lifetime |
| Component leads, terminations, lugs and wires | J-STD-002, specified revision, method and applicable component specification | Package solderability results tied to the part number, termination finish and lot | Solderability of the mating PCB pads |
| Whether a surface accepts solder | Applicable visual immersion, process simulation or wetting balance method | Coverage/feature observations or force-time records under the stated conditions | Resistance to every subsequent thermal or mechanical load |
| Whether an item survives soldering heat | Applicable solder heat resistance test or component qualification requirement | Electrical, physical or structural results after the defined exposure | Automatic acceptance of its surface wetting behavior |
| Whether an assembled joint will survive service | Product-specific reliability qualification | Results under the relevant thermal, mechanical and electrical stresses | A replacement for incoming material controls |
Use J-STD-003 for printed boards and J-STD-002 for component leads and terminations; confirm the contractually applicable revision (including whether J-STD-003D and J-STD-002E remain current at the date of procurement). The public J-STD-003D scope also separates coating durability from product Class: ordering Class 3 does not, by itself, define every conditioning parameter. Use the revision and test conditions named in the purchase agreement. The public previews identify scope and methods; the applicable full standard is needed to execute and judge the test. IPC revision table, J-STD-003D scope, J-STD-002E scope.
What does each solder test actually measure?
Visual immersion tests expose the designated surface to flux and molten solder, then inspect the required features for wetting, nonwetting or dewetting. Inspection must identify the area being judged; a whole-board average can conceal a failed individual land or termination.
Surface mount process simulation uses the specified paste and thermal procedure to evaluate the relevant solderable features. It can address a different question from immersion testing, so the method cannot be silently substituted when a purchase order names another test.
PCB wetting balance testing records force against time during controlled solder contact. It provides a curve for comparing wetting behavior, provided specimen geometry, conditioning, alloy, flux and test settings are controlled. A curve without those settings is difficult to compare with another laboratory's result.
Solder globule testing brings a small component termination into contact with a controlled molten solder globule. It is useful where the termination geometry calls for that arrangement. It is not a general test of unwanted solder-ball formation on a PCB. Fraunhofer ISIT describes both bath and solder-ball contact arrangements for wetting-force measurement. Fraunhofer ISIT method overview.
A solder float test needs its purpose stated explicitly. A solderability procedure and a thermal-stress examination may both involve contact with molten solder, but their exposure and acceptance criteria differ. For a solder float test on a PCB, request the named method, board construction, dwell conditions and observations. Do not substitute a familiar bath temperature for the specified procedure.
Why must temperature, dwell and acceptance criteria stay together?
A number such as “95% covered” is useful only when its test object and procedure are known. The following published component example shows why solderability testing and resistance to soldering heat need separate entries in the test plan.
| Vishay RCG e3 chip resistor test | Published bath conditions | Published result being evaluated |
|---|---|---|
| Solderability with tin-lead solder | Sn60Pb40; non-activated flux; 235 ±5°C for 2 ±0.2 seconds | At least 95% solder coverage and no visible damage |
| Solderability with lead-free solder | Sn96.5Ag3Cu0.5 or Sn99.3Cu0.7; non-activated flux; 245 ±5°C or 250 ±5°C for 3 ±0.3 seconds, as listed in the datasheet | At least 95% solder coverage and no visible damage |
| Resistance to soldering heat | Solder bath at 260 ±5°C for 10 ±1 seconds | Resistance-change limits for the stated stability class; this is a different acceptance row |
Source: Vishay RCG e3, Document 20047, revision 08-Nov-2023, page 5. These conditions apply only to that Vishay component family and its referenced test schedule, which should be checked against the current revision before use. They are not universal bare-board limits, reflow profiles or HILPCB production settings. Keep the two listed lead-free alloys and temperature options with the manufacturer's procedure rather than inventing a pairing or choosing a convenient temperature.
How should PCB wetting testing results be read?
A wetting balance measures net force under a defined immersion geometry; the expression below is a simplified static model rather than a complete dynamic wetting-force measurement. After the specimen weight is tared, a simplified static force model, with downward wetting force taken as positive, is:
F = γP cos(θ) − ρgV
Here F is measured force in newtons, γ is solder surface tension in N/m, P is the wetting perimeter in metres, θ is the contact angle, ρ is solder density in kg/m³, g is gravitational acceleration in m/s², and V is immersed volume in m³. The second term is buoyancy. Instruments may display the opposite sign convention.
IPC-TM-650 2.4.14.2A explains the buoyancy-corrected reference for wetting time and maximum force. Its scope is liquid flux activity, so its physics explanation must not be mistaken for a blanket PCB acceptance specification. Changing immersion depth or specimen size changes the buoyancy correction and can also change heat transfer. An uncorrected instrument-zero crossing is therefore not interchangeable with a specified corrected wetting time. IPC-TM-650 2.4.14.2A, pages 2–3.
A simple comparison illustrates the perimeter issue. Suppose two measurements have already been corrected for buoyancy and have matched test conditions: specimen A gives 3 mN over a 10 mm wetting perimeter, while specimen B gives 1.5 mN over 5 mm. Both give 0.30 mN/mm. The larger raw force does not establish better surface wetting. These are hypothetical measurements, not an acceptance limit; different thermal mass can still prevent a direct comparison.
Request the raw curve, instrument zero and corrected reference, wetting perimeter, immersed volume/depth, immersion speed, alloy, bath temperature, flux and conditioning record. The agreed method should define which times and forces are evaluated. Neither “under one second” nor a single force-per-perimeter value is a universal pass criterion.
Does steam aging predict shelf life?
Conditioning challenges a finish under a defined exposure. It does not, without a validated correlation for that material and storage environment, convert test hours into months on a warehouse shelf.
J-STD-003D identifies different coating-durability and conditioning arrangements. Select the required condition for the actual finish and order; do not apply a single steam recipe to HASL, OSP, ENIG and every component termination. Also distinguish chamber qualification from specimen conditioning: IPC-TM-650 2.6.23, dated July 1993, records steam-ager temperatures every 15 minutes for 8 hours after stabilization, with no other components inside. That eight-hour measurement checks equipment repeatability; it is not a universal eight-hour product-aging requirement. IPC steam-ager repeatability method, section 5.3.
For stored boards, retain the finish supplier's packaging and storage instructions, fabrication date, bag-opening history, environment and any bake or reflow exposure. OSP chemistry and the actual thermal profile matter more than a generic promised number of reflow cycles. For ENIG, thickness and nickel-interface condition are separate evidence needs: passing wetting results alone does not rule out nickel corrosion or prove joint fracture resistance. Do not substitute an extended solder dwell for an appropriate finish investigation.
What should a solderability test procedure and report contain?
The test plan should be agreed before the laboratory receives samples. Otherwise, two valid-looking reports may describe different questions.
| Required record | Detail that makes the result usable |
|---|---|
| Identity and sampling | Board revision or component part number; finish/termination; manufacturing lot; sampling locations and rationale; number of independent specimens |
| History | As-received condition, packaging, storage, prior thermal exposures and every cleaning or conditioning step |
| Procedure | Standard revision, method, deviations, test alloy/flux, temperature, dwell, immersion geometry and equipment identification |
| Acceptance | Feature or termination being judged, criterion and source; how individual failures affect the sampled lot |
| Results | Individual observations, images and raw curves where applicable; dimensions and corrections needed to interpret the measurement |
| Disposition | Acceptance decision, retained samples, nonconformance reference, approved retest/rework route and release authority |
Five samples do not automatically provide a useful “95% confidence” guarantee. For illustration, assume five independent randomly selected units from a large, uniform population, each scored pass/fail, with no failures observed. A one-sided exact 95% upper bound on the failure probability is 1 − 0.05^(1/5) = 45.1%. This is a sampling calculation, not a recommended acceptance plan. Samples from one convenient corner of a panel may not even satisfy those assumptions. Choose the sampling plan around the specified lot and decision risk.
What happens when a lot fails solderability screening?
Hold the affected material and preserve the as-received evidence. First check whether the test was executed correctly: specimen preparation, flux, bath condition, temperature, fixture geometry and timing can affect the result. If the failure is valid, compare the board and component lots, finish history, storage and assembly records before assigning a cause.
| Observation | Next evidence to obtain | Avoid this shortcut |
|---|---|---|
| Poor wetting on a stored board lot | Finish/packaging history, representative feature results and supplier investigation | Raising temperature until a specimen passes |
| Component terminals fail while board coupons pass | Component lot/date code, termination finish and the applicable component test | Treating the PCB result as component acceptance |
| Wetting passes but joints fracture | Interface examination and mechanical/reliability evidence appropriate to the failure | Declaring black pad or another mechanism excluded by a wetting pass |
| Assembly shows cold solder or incomplete joints | Actual thermal profile, paste/flux, printing, placement and material evidence | Assuming every assembly defect proves poor incoming solderability |
Cleaning, plasma treatment, chemical treatment, refinishing or a more active flux changes the tested condition. Such measures need an approved process and an evaluation of their effect on the finish, dimensions, residues and assembly. Retesting treated samples does not erase the original failure or authorize release of untreated stock.
What should be included in a HILPCB testing request?
HilPCB offers wetting-balance and solderability testing for board finishes and component leads. Scoped methods can include surface analysis by SEM/EDS or contact angle, conditioning, incoming pad/lead/finish checks, controlled profiling, and SPI/AOI correlation. Sampled FAI microsections, lot segregation, FIFO/barcode-linked records, failure analysis, and approved cleaning or refinish process support are available. Test reports may include raw wetting curves, statistics and photos within the agreed sampling and report scope; no universal shelf-life, every-lot cross-section or zero-defect guarantee is implied.
Our engineering team reviews designs for solderability risk factors including pad geometries, mask definitions, and finish specifications. We maintain extensive databases correlating design features with solderability performance.
Our laboratory features multiple wetting balance systems, steam aging chambers, and surface analysis equipment.
Send the fabrication drawing and finish requirement, assembly process and alloy, component BOM where relevant, lot/storage information, required standard revision/method, sampling plan and reporting requirements. Identify whether the concern is incoming material, a finish change, expired storage guidance or a production defect. For small-batch assembly or volume assembly, carry the approved lot disposition and test requirements into the handoff; identify sourcing responsibilities for turnkey assembly.
For SMT assembly or through-hole assembly, ask HILPCB to confirm the test execution location, available method, sample consumption, report content, price and schedule in the quotation. Name any requirement for an external laboratory, raw wetting curves, microscopy or additional analysis. A general PCB assembly order should not be assumed to include every specialized laboratory test or a cross-section of every lot.
Frequently asked questions
What is the difference between solderability testing and solder testing after assembly?
Solderability testing evaluates whether designated surfaces accept solder under specified conditions. Post-assembly solder testing may inspect workmanship, electrical continuity or joint reliability. The intended result determines the method; a passing surface test does not replace finished-assembly inspection and qualification.
How do I choose a solderability test for PCB pads and component leads?
Define them as separate test objects. J-STD-003 addresses printed boards, while J-STD-002 addresses component leads and terminations. Select the applicable revision, method, conditioning and acceptance criteria for each. Package geometry and the supplier's component specification also affect the choice.
Is a solder float test enough to qualify a board for assembly?
Only for the decision covered by the named test and acceptance criteria. State whether the float is evaluating solderability or thermal stress, and record the prescribed exposure and inspected features. It does not independently qualify every component, assembly process or service-life requirement.
How to evaluate solderability compatibility after surface finishing on PCB connectors?
Separate the connector's solderable leads from its mating contacts, and separate PCB solder lands from plated edge fingers. Check the specified termination finish, board finish, alloy, flux and assembly exposure at the soldered interface. Gold-plated wear contacts are not surfaces that must all accept solder. Require the relevant board and component results, then validate the intended assembly process.
Does a passing wetting balance curve rule out cold solder joints?
No. A curve describes the tested surface under laboratory conditions. Cold solder joints and other assembly defects can also arise from insufficient heating, process variation or movement during solidification. Investigate the actual assembly conditions and inspect the finished joints.
Can an old PCB lot be released after cleaning and retesting?
Only under an approved disposition that covers the original failure, treatment, new test condition and applicable assembly requirements. Confirm the supplier's storage guidance and retain the initial results. A treated sample passing a different condition is not evidence that all untreated boards remain acceptable.