8-layer stackup example: your first lesson in material parameters and stackup planning

Hi, I’m an instructor at the HILPCB Stackup & Materials Academy. In daily work I see many excellent hardware engineers who are comfortable with schematics, but when they turn design intent into a physical PCB, stackup design often becomes the bottleneck. How do Dk/Df values affect signals? Why does CTI matter for safety compliance? Will 2oz copper create manufacturing challenges?

Today, we’ll use a classic 8 layer stackup example to break down the full path from material selection to manufacturing delivery. This is not only a pcb stackup tutorial—it’s a first lesson in building a standardized, mass-producible stackup knowledge base for you and your team.

Where stackup design starts: define inputs and expected outputs

A professional stackup is never a random pile of signal and plane layers. It starts with clear engineering requirements and ends with a precise manufacturing guidance document.

Inputs:

1. Signal rate & type (Signal Integrity):

   • What is the highest frequency / data rate? (e.g., 10Gbps PCIe, 480Mbps USB 2.0)
   • Which impedances must be controlled? (e.g., 50Ω single-ended, 90/100Ω differential)
   • What are the crosstalk and loss budgets for critical nets?

2. Current & power (Power Integrity):

   • What is the maximum operating current? Which nets carry high current?
   • What is the IR drop budget for power planes?
   • This directly drives high current copper balancing and copper thickness selection.

3. Thermal management:

   • Which devices are the primary heat sources, and what is their power?
   • What is the ambient environment? Do you need high-Tg materials or a metal core?

4. Compliance & reliability:

   • What is the application environment? (e.g., industrial, medical, consumer)
   • Any special requirements on CTI (Comparative Tracking Index)?

Outputs:

Ultimately, you should provide your PCB manufacturer with a stackup drawing that includes:

• Layer type for each layer (Signal, Plane, Solder Mask, etc.)
• Material grade/model (e.g., Shengyi S1000-2M)
• Copper thickness (e.g., Hoz, 1oz, 2oz)
• Dielectric thickness (Core and PP/prepreg)
• Target impedance and corresponding trace width/spacing
• Total board thickness and tolerance

Material parameter quick reference: choosing between FR-4 and high-speed materials

Selecting the right laminate is the first step of stackup design. Different materials vary widely in electrical performance, thermal performance, and cost. The table below compares several common options to help you quickly narrow down. To match a laminate to its IPC slash sheet, see our IPC-4101 specification guide.

Instructor notes:

• Dk: Lower Dk means faster propagation; for the same impedance you can use wider traces, which helps manufacturability. A Dk 3.66 material typically outperforms Dk 4.2.
• Df: Dk drives speed; Df drives attenuation. For >5Gbps links, Df < 0.010 is a practical starting point.
• Tg: Higher Tg reduces deformation during high-temperature processes (e.g., lead-free reflow) and improves reliability. Tg ≥ 170°C is commonly considered “high Tg”.
• CTI: Measures resistance to tracking under moisture/contamination. PLC 3 (175–250V) is baseline; PLC 1 (>400V) or PLC 0 (>600V) is often required for high-voltage or strict compliance designs.

A core stackup paradigm: evolving from 4 layers to 8 layers

Once materials are selected, the next step is to “build” the PCB. A few golden rules apply: keep signal layers adjacent to reference planes, couple power and ground planes, and use symmetry to prevent warpage.

Paradigm 1: the classic four layer impedance control

This is the most common 4-layer impedance-controlled stackup, suitable for many IoT modules and simple controllers.

• L1: Signal + Component
• L2: GND Plane
• L3: Power Plane
• L4: Signal

Pros: Simple structure and low cost. You can achieve accurate impedance control for L1/L4 microstrips and stripline routing referenced to L2/L3. Cons: Larger spacing between power and ground reduces plane capacitance and weakens high-frequency decoupling. EMI shielding is moderate.

Paradigm 2: the classic 8 layer stackup example

This is an excellent balance of performance, cost, and layer count. It’s widely used in computer motherboards, high-end routers, and complex industrial control boards.

Layer	Type	Function & design notes	Typical copper
L1	Signal	Top-layer signals and main components. Route high-speed nets (e.g., USB, HDMI).	1 oz
L2	GND	Primary reference plane. Provides a low-inductance return path for L1 and shields internal noise.	1 oz
L3	Signal	Inner signals—often for mid/low-speed nets or stripline routing of high-speed signals.	0.5 oz (Hoz)
L4	Power	Main power plane. Tightly coupled with L5 GND to provide low-impedance distribution.	1 oz
L5	GND	Secondary ground plane. Couples with L4 to form plane capacitance and improve HF decoupling.	1 oz
L6	Signal	Inner signals—symmetric with L3—for routing or secondary power splits.	0.5 oz (Hoz)
L7	Power	Secondary power plane or power segmentation.	1 oz
L8	Signal	Bottom-layer signals and secondary components.	1 oz

The essence of this 8 layer stackup example:

1. Signal/reference alternation: Each signal layer (L1, L3, L6, L8) is adjacent to a reference plane (L2, L4, L5, L7) for a solid return path.
2. GND shielding: L2 and L5 “sandwich” the core high-speed layer (L3) and power plane (L4), delivering strong EMI shielding.
3. Power/GND coupling: L4 and L5 are closely spaced, creating large plane capacitance—critical for overall PI.
4. Symmetry: The structure is symmetric around the center (between L4/L5), helping control warpage during lamination and reflow.

Practical pairing rules for signals, power, and copper thickness

High-speed signals: a mini hdmi pcb stackup guide

For HDMI or PCIe-class high-speed differential pairs, stackup design should focus on:

• Continuous reference planes: Keep an unbroken reference plane under the pair—avoid crossing splits.
• Dielectric thickness: The L1–L2 dielectric thickness drives trace width and impedance. For example, with S1000-2M, to achieve 100Ω differential impedance at 4mil (0.1mm) dielectric thickness, the width/space might be ~5mil/5mil.
• Glass weave effects: For >10Gbps, standard glass styles (e.g., 1080) can introduce Dk non-uniformity and timing jitter. Consider flatter glass styles (e.g., 106, 1035) or glass-weave mitigation routing.

High current: the art of high current copper balancing

When your design carries tens of amps:

• Copper thickness: 1 oz (35um) is standard, but high-current paths may need 2 oz (70um) or even 3 oz (105um).
• Symmetry matters: If L4 uses 2 oz copper, the symmetric L5 is best kept at 2 oz as well—even if it’s “just GND”. This high current copper balancing is key to preventing “potato-chip” warpage during fabrication and assembly.
• Heat spreading on inner planes: Thick inner planes are excellent heat spreaders; use Thermal Vias to conduct heat from devices into inner copper.

Hybrid lamination and specialty materials: beyond standard FR-4

Sometimes one material cannot satisfy every requirement. RF sections may need ultra-low loss materials, while digital control can remain on FR-4.

• Rogers + FR-4 hybrid: Use Rogers (e.g., RO4350B, Dk=3.66) on the outer RF layers and FR-4 elsewhere to balance performance and cost. This requires tight hybrid-lamination process control.
• HDI: When routing density is extreme, HDI uses laser-drilled Microvias. This is a broader hdI stackup tutorial topic; the core is the build-up method (e.g., 1+N+1 or 2+N+2) and demands deep alignment with your manufacturer.
• MCPCB: For high-power LED or power modules, Aluminum Core (MCPCB) provides exceptional thermal performance.

Manufacturing impact: the “last mile” from drawing to finished board

Even a perfect stackup is only paper if it cannot be manufactured consistently.

How HILPCB simplifies your stackup design

Theory matters, but practical tools and expert support make execution efficient. At HILPCB, we’re not only a manufacturer—we’re your stackup partner.

For many teams, maintaining a large, validated material/stackup library is a major challenge. MOQ, lead times, and small differences between suppliers all introduce uncertainty.

HILPCB’s Stackup Claim Service is built to address that pain. We stock common and specialty materials—from standard FR-4 to Rogers and TACONIC—so your design can always find the best, immediately available physical platform. Our impedance test lab provides data support for every production batch.

From understanding the nuances of Dk/Df, to planning a robust 8 layer stackup example, to anticipating manufacturing constraints—stackup design is an art that bridges theory and practice. I hope this lesson opens a window and helps you design with more confidence.

Conclusion

This article used an 8 layer stackup example to explain material parameters, stackup planning, impedance/thermal/cost trade-offs, and manufacturing considerations. With the checklist and process windows in this guide—and with early involvement from HILPCB’s DFM/DFA team—you can accelerate prototypes and mass production while maintaining quality and compliance.

If you need fabrication and assembly support, contact HILPCB Turnkey Assembly or SMT Assembly for DFM/DFT recommendations.

Common Questions

Why is an 8 layer stackup example useful for PCB teams?

An 8 layer stackup example gives teams a practical reference for arranging signal, plane, and power layers in a balanced way. It helps translate abstract stackup theory into a manufacturable starting point for real projects.

Why do Dk, Df, and material selection matter so much?

Dielectric constant and loss factor directly affect impedance, delay, and signal attenuation. Choosing the wrong material can undermine high-speed performance, even if the routing looks correct on paper.

Why must impedance, thermal behavior, and cost be balanced together?

Stackup design is rarely about one target only. A structure optimized only for impedance may increase cost or hurt thermal performance, so engineers need trade-offs that work across electrical, mechanical, and manufacturing goals.

Why should PCB manufacturers join stackup planning early?

Early DFM/DFA input helps confirm material availability, process windows, and realistic tolerances before the design is frozen. That reduces respins and makes prototype-to-production transfer much smoother.

Related links

• ipc 4101 specification guide: 20 stackup & material faqs
• Turnkey Assembly
• SMT Assembly