An AC-DC converter PCB converts mains-frequency AC into regulated DC while containing hazardous energy, switching noise and heat within defined safety and performance limits. A successful board is therefore not just a rectifier plus regulator: it is a coordinated insulation, power-loop, control, thermal, EMC and production system.
Key Takeaways
- Freeze the end-equipment safety standard, insulation boundary, input range, altitude, pollution degree and overvoltage category before setting PCB spacing.
- Clearance is the shortest air path and is driven mainly by impulse voltage and altitude; creepage is the shortest surface path and depends on working voltage, pollution degree and material group.
- Select flyback, forward, LLC or bridge-derived stages from power, isolation, load range, hold-up, transient and cost requirements—not from peak efficiency alone.
- Treat PFC as an input-current-shaping and harmonic-compliance stage. It is not a multiplier that can simply be applied to conversion efficiency.
- Minimize high-
di/dtloop area, minimize high-dv/dtcopper area and keep sensing/control paths out of both fields. - Keep the mains filter physically and electrically separated from noisy converter nodes; uncontrolled parasitic capacitance can bypass an otherwise correct filter.
- Copper weight, pours and thermal vias help only when the complete current and heat paths are modeled and manufactured consistently.
- SiC and GaN reduce device switching loss in suitable designs but make commutation inductance, common-mode current, gate-loop layout and measurement method more critical.
- Release the PCB against evidence at input, load and environmental corners; a nominal bench waveform is not a production qualification.
Table of Contents
- Define the Converter Before Choosing a Topology
- Choose an AC-DC Power Architecture
- Design the Safety and Isolation Boundary
- Partition the PCB Around Current and Field Paths
- Lay Out PFC and Main Switching Stages
- Control Conducted and Radiated EMI
- Use SiC and GaN Without Losing Margin
- Close the Thermal and Current-Carrying Design
- Plan Distributed Power and Point-of-Load Conversion
- Use an AC-DC Converter Release Matrix
- Diagnose Common Prototype Failures
- AC-DC Converter PCB RFQ Checklist
- Reference Standards and Responsibility Boundaries
- How HILPCB Supports Power Converter Builds
- FAQ
- Conclusion
Define the Converter Before Choosing a Topology
Start with a signed electrical and environmental specification. Otherwise, topology, spacing and thermal decisions will be optimized against different assumptions.
| Requirement group | Inputs that must be explicit | What it controls on the PCB |
|---|---|---|
| Mains input | Nominal/range, frequency, phase, brownout, surge and inrush | Rectifier, protection, bulk capacitor, conductor stress and spacing |
| DC output | Voltage, current, ripple, dynamic load and startup sequence | Topology, magnetics, rectification, control and copper distribution |
| Isolation | Functional, basic, supplementary or reinforced; accessible circuits | Transformer, slots, creepage, clearance, optocoupler/digital isolator and test |
| Load profile | Minimum, typical, peak, duration and standby modes | Efficiency weighting, burst behavior, thermal cycling and hold-up |
| Environment | Ambient, airflow, enclosure, altitude, humidity and pollution degree | Derating, cooling, clearance correction and contamination risk |
| Compliance | Product safety, harmonic current, emissions, immunity and efficiency program | Filter, PFC, insulation coordination, test access and documentation |
| Lifetime | Mission profile, cycles, serviceability and allowed failure behavior | Component stress, electrolytic selection, thermal margin and protection |
The most useful efficiency number is not always the highest point on a curve. Calculate losses across the actual operating histogram. For a fixed DC output power Pout, annual input-energy difference between two efficiencies is:
ΔE = Pout × hours × (1/η1 − 1/η2)
This calculation is valid only when load, input and cooling assumptions are the same. Add cooling or facility effects separately instead of hiding them in a marketing ROI percentage.
Choose an AC-DC Power Architecture
An offline supply commonly includes protection and inrush control, EMI filtering, rectification, optional PFC, an isolated DC-DC stage, secondary rectification and output filtering. The topology table narrows the design space; controller and semiconductor reference designs then establish the detailed operating limits.
| Main conversion choice | Where it is often useful | Main PCB challenge | Decision warning |
|---|---|---|---|
| Flyback | Lower-power, isolated, cost-sensitive outputs | Leakage-energy clamp, primary/secondary hot loops and transformer capacitance | Power level alone does not determine suitability; verify stress, temperature and EMI |
| Forward-derived converter | Moderate power where transformer use and predictable current matter | Reset/clamp loop, rectifier loop and magnetics placement | Include reset conditions and switch/diode stress at line and load corners |
| LLC resonant half bridge | Efficient isolated conversion around a designed gain window | Resonant loop, half-bridge node, gate drive, sensing and light-load behavior | Do not select from one peak-efficiency point; check gain range, ZVS region and burst mode |
| Phase-shifted full bridge | Higher-power isolated systems with controlled soft switching | Two commutation legs, transformer loop, circulating current and synchronous rectification | Light-load switching and device stress can dominate outside the target window |
| Interleaved stages | Higher current or ripple cancellation requirements | Current sharing, phase symmetry, coupled EMI and thermal balance | Cancellation depends on tolerance and control; one phase fault changes stress sharply |
PFC may be separate or integrated with the main stage. Continuous-conduction boost PFC is common at higher power because it can limit current ripple, while critical- and discontinuous-conduction approaches trade peak current, switching frequency range and EMI differently. The correct boundary depends on the controller, power range and compliance target.
Design the Safety and Isolation Boundary
Do not start high-voltage spacing with an IPC table alone. The applicable end-equipment standard and insulation coordination define the boundary.
Clearance is the shortest distance through air. Required clearance is associated with transient/impulse voltage, field conditions, pollution degree and altitude. Above the reference altitude used by the standard, a correction factor may be required.
Creepage is the shortest path along an insulating surface. Required creepage depends on RMS working voltage, pollution degree, insulation grade and material group derived from comparative tracking index (CTI).
| Boundary question | Evidence needed before layout release |
|---|---|
| Which circuits are hazardous and which are accessible? | Product safety classification and system block diagram |
| What insulation grade separates them? | Functional/basic/supplementary/reinforced requirement |
| What voltage dimensions clearance? | Required impulse/transient voltage and altitude |
| What voltage dimensions creepage? | Highest relevant working voltage, including repetitive waveform conditions |
| What surface assumptions apply? | Pollution degree, material group, coating qualification and slot geometry |
| Can a component bridge the boundary? | Component insulation rating, package distances and certification scope |
| How will production verify it? | Controlled artwork, routing rule report, inspection and dielectric test plan |
A milled slot can increase the surface path only when its width and geometry qualify under the selected standard. Solder mask, conformal coating and potting do not automatically create reinforced insulation; their material, process, thickness, coverage and qualification must be accepted by the product safety assessment.
Keep the primary-to-secondary boundary visible across every layer. Review copper, pads, vias, mounting hardware, heatsinks, shields, test points, transformer pins and assembly tolerances—not only top-layer traces.
Partition the PCB Around Current and Field Paths
The schematic shows connectivity; the layout creates parasitic resistance, inductance and capacitance. Mark these paths before placement:
- High-
di/dtloops: rectifier/bulk charging, PFC commutation, half-bridge commutation, transformer-primary switching and secondary rectification. - High-
dv/dtnodes: MOSFET drains, half-bridge switch node, transformer windings and snubber nodes. - High-current paths: input bridge, bulk bus, transformer and output distribution.
- Quiet paths: current shunt Kelvin sense, voltage feedback, compensation, zero-current detection and controller reference.
- Heat paths: semiconductors, magnetics, bridge rectifier, shunts, capacitors and connectors into copper, heatsink, chassis or airflow.
Place large power components in energy-flow order, reserve a quiet controller area, then route power loops before signal traces. Minimize commutation loop area, but do not enlarge a switch-node pour merely to reduce resistance or spread heat: more high-dv/dt surface increases capacitive coupling and common-mode current.
Use Kelvin connections directly at a current shunt's sense terminals. A wide power trace with sense lines tapped downstream measures trace and via drop as well as the shunt. Keep controller bypass capacitors and gate-loop parts at the pins specified by the device manufacturer.
Ground labels are not proof of a low-impedance return. Define power return, controller reference, chassis/protective earth and secondary return by current path, then connect them at intentional points supported by the controller and EMC architecture.
Lay Out PFC and Main Switching Stages
PFC shapes input current so the supply can meet power-factor and harmonic-current goals. It does not turn apparent power into conversion efficiency, and its requirement depends on product class, power and market.
For a boost PFC stage:
- Keep the MOSFET, boost diode and high-frequency capacitor commutation loop compact.
- Keep the switch-node copper no larger than electrical and thermal requirements demand.
- Route shunt/current-transformer sensing as a quiet Kelvin pair away from gate and drain fields.
- Separate the PFC output-voltage divider and compensation network from switching nodes.
- Place the gate driver and its return close to the switch; check turn-on and turn-off loops separately.
- Keep the input filter's line and converter sides from crossing or coupling around the filter.
For LLC stages, preserve the intended resonant loop and controller-sense network. Half-bridge gate drive, bootstrap path, resonant-current sensing and feedback components need the controller vendor's placement rules. Signal ground and power ground may require a defined single-point connection at the bulk-capacitor return; a generic split-ground rule is unsafe.
The transformer is both a power component and a common-mode coupling path. Winding construction, interwinding capacitance, shield strategy and primary-to-secondary PCB geometry must be evaluated together.
Control Conducted and Radiated EMI
EMI debugging is faster when noise source, coupling path and victim are separated. The input filter cannot correct every layout-generated path.
| Symptom or observation | Likely path | Discriminating action |
|---|---|---|
| Conducted peak moves with switching frequency | Differential-mode commutation current | Probe hot loop and compare LISN result with loop/snubber changes |
| Similar noise appears on line and neutral | Common-mode displacement current | Measure common-mode current and inspect switch-node-to-chassis/secondary capacitance |
| Filter works in simulation but not hardware | Input/output coupling bypasses filter | Inspect placement, plane overlap, choke pin orientation and cable routing |
| Controller resets at a switching edge | Ground/reference or capacitive injection | Probe pin-to-local-ground with a short connection; inspect return and filtering |
| EMI changes when the heatsink is touched or bonded | Heatsink capacitance and grounding | Compare defined floating/bonded configurations and safety implications |
| Radiated result depends on enclosure/cable position | System common-mode antenna | Reproduce final harness, chassis, shield and protective-earth arrangement |
Place the EMI filter away from switch nodes and magnetics. Do not route a plane under the filter if it couples noisy converter-side voltage to the clean input side. Keep common-mode choke input and output conductors from crossing. Validate X/Y capacitor safety class and discharge requirements at the system level.
Snubbers, gate resistors and ferrites change loss and stress as well as emissions. Tune them from measured waveforms using a probe setup whose loop inductance and bandwidth are known.
Use SiC and GaN Without Losing Margin
Wide-bandgap devices can reduce switching loss and enable higher frequency, but their faster edges expose parasitics that slower silicon designs may tolerate.
- Minimize the complete commutation loop, including capacitor terminals, package inductance and vias.
- Separate gate power and source/Kelvin-source returns when the package supports it.
- Control gate resistance and turn-on/turn-off paths according to the device and driver data.
- Check negative gate transients, false turn-on, overshoot, ringing and common-mode current at worst line/load/temperature.
- Keep switch-node copper controlled; a larger pour can worsen displacement current even if it improves heat spreading.
- Use differential probes, current probes and de-embedding appropriate to the edge rate. A long probe ground lead can create the ringing being “measured.”
Do not claim that a driver loop is acceptable merely because its estimated inductance is “nanohenry-level.” Correlate extracted geometry, measured switching behavior, device limits and EMC results.
Close the Thermal and Current-Carrying Design
Board copper is one branch of a thermal network, not a universal heatsink. Estimate losses for semiconductors, magnetics, capacitors, shunts and conductors across line/load corners, then verify temperature in the final airflow and enclosure.
Heavy copper can reduce conductor resistance and spread heat, but it also changes etching limits, spacing, via transition design, soldering thermal balance and cost. Specify copper by layer and finished requirement. For heavy copper PCB manufacturing, confirm trace geometry, current, temperature rise and assembly process together.
Thermal vias are effective only when their diameter, plating, pitch, connected copper and receiving heat path are defined. Avoid plane cuts that block lateral spreading. Do not use a high-dv/dt switch node as a large thermal plane without analyzing the EMI consequence.
Electrolytic-capacitor life depends strongly on hotspot temperature and ripple current. Magnetics require winding/core loss and local airflow assessment. Connector and terminal heating can dominate even when the board trace calculation passes.
Plan Distributed Power and Point-of-Load Conversion
In server and telecom equipment, an AC-DC front end may feed an intermediate bus such as 48 V or 12 V, followed by non-isolated point-of-load converters. This architecture can reduce long low-voltage/high-current paths and support modular redundancy, but it does not make redundancy automatic.
Define:
- current sharing and ORing behavior;
- hot-swap/inrush control;
- hold-up and ride-through allocation;
- fault containment and protection coordination;
- bus capacitance and connector limits;
- telemetry, sequencing and standby power;
- efficiency across the complete AC-to-load chain.
An N+1 label is only meaningful when failure detection, isolation, replacement behavior and common-cause risks have been validated. A point-of-load failure can still collapse a shared bus if protection is not coordinated.
Use an AC-DC Converter Release Matrix
This matrix converts power-supply development from a collection of waveforms into a controlled release decision.
| Release gate | Controlled inputs | Required evidence | Stop condition |
|---|---|---|---|
| Requirements | Input/output, mission profile, isolation, environment and standards | Approved compliance and derating plan | Product class or insulation boundary is unresolved |
| Architecture | Topology, controller, devices, magnetics and protection | Corner analysis, stress/loss budget and fault concept | Any component exceeds rating or control range |
| PCB release | Stackup, spacing rules, hot loops, fields, thermal path and test access | Schematic/layout review plus manufacturing drawing | Unrouted safety rule, ambiguous copper or inaccessible critical node |
| Engineering prototype | Controlled BOM and setup | Startup, steady-state, transient, protection, thermal and preliminary EMC data | Unsafe behavior, unstable loop or uncontained fault |
| Compliance prototype | Production-intent board, enclosure, cables and firmware | Safety, harmonic, emissions/immunity and dielectric evidence | Test setup or sample differs materially from release build |
| Pilot production | Approved materials, assembly process and end-of-line test | Yield, capability, traceability and failure disposition | Substitution or process drift invalidates qualification |
At each gate, test high/low input, minimum/typical/maximum load, startup/shutdown, brownout, short/open faults and thermal extremes that apply. Archive schematics, PCB revision, BOM, firmware, probe setup and raw data so a later change can be assessed against the qualified baseline.
Diagnose Common Prototype Failures
| Failure | Common root causes | Next useful evidence |
|---|---|---|
| MOSFET overshoot or ringing | Commutation inductance, diode recovery, transformer leakage or probe artifact | Differential voltage plus loop-current measurement and layout extraction |
| PFC current distortion | Sense pickup, control saturation, poor input sampling, inductor behavior or line filter interaction | Line/current waveform, sense pin and controller state across line/load |
| LLC loses ZVS | Gain range, magnetizing/resonant design, dead time, load or parasitic mismatch | Switch-node, resonant current and gate timing across corners |
| EMI filter underperforms | Bypass capacitance, choke coupling/orientation, layout overlap or wrong mode diagnosis | Separate common- and differential-mode measurements |
| Feedback is noisy or unstable | Incorrect return, optocoupler/compensation behavior, switch-node coupling or inadequate bypass | Loop response and pin waveforms referenced at local ground |
| Board passes open-bench thermal test but fails enclosed | Recirculation, magnetics/capacitor hotspot, blocked plane or interface resistance | Temperature map in final mechanical configuration |
| Dielectric or spacing failure | Wrong insulation assumptions, contamination, burr/slot issue or component boundary | Safety-rule audit, controlled inspection and test record |
AC-DC Converter PCB RFQ Checklist
Electrical specification: input range/frequency, output rails and tolerances, continuous/peak load, ripple, transient response, hold-up, standby, efficiency targets, PFC/harmonic targets and protection behavior.
Safety and environment: target markets and end-equipment standards, insulation diagram, working/impulse voltages, overvoltage category, pollution degree, material group/CTI assumptions, altitude, humidity, ambient, airflow, enclosure and protective-earth/chassis strategy.
Design package: schematic, Gerber/ODB++/IPC-2581, stackup, copper by layer, net-class spacing rules, controlled slots, transformer/magnetics documents, critical footprints, assembly drawings and approved BOM/alternates.
Power and thermal data: RMS/peak currents, expected losses, hotspot limits, heatsinks/interfaces, thermal-via construction, conductor temperature-rise criteria and mechanical keep-outs.
Test and compliance: dielectric/ground-bond requirements, functional test limits, programming, fixtures, probe/test points, surge/inrush, harmonic current, conducted/radiated EMC, immunity and sample plan.
Production controls: lot traceability, critical component substitutions, material change rules, cleanliness/coating requirements, inspection class, AOI/X-ray needs, first-article report and requalification triggers.
Reference Standards and Responsibility Boundaries
- IEC 60664-1 — IEC
- IEC 62368-1 — IEC
- IEC 61000-3-2 — IEC
- CISPR 32 — CISPR
- IEC 62109-1 — IEC
- IEC 61800-5-1 — IEC
- IPC-2221 — IPC
- IPC-9592 — IPC
- IPC-6012 — IPC
- IPC-A-600 — IPC
- IPC-A-610 — IPC
The applicable standards depend on product type, market, voltage, installation and use environment. A PCB manufacturer can build controlled geometry, materials and workmanship and can support DFM, coupons and assembly evidence. The product owner and designated certification body remain responsible for circuit architecture, safety classification, component approval, protection, EMC, thermal limits, firmware, final enclosure and end-equipment qualification.
How HILPCB Supports Power Converter Builds
HILPCB can review stackup, copper distribution, high-current transitions, spacing artwork, routed slots, thermal-via construction, solderability and assembly access before fabrication. Multilayer PCB manufacturing supports controlled power/return structures, while high-thermal PCB options can be evaluated where the electrical insulation and assembly requirements permit them.
For production-intent prototypes, turnkey PCB assembly can align the approved BOM, polarity/orientation controls, inspection and traceability with the released board revision. Exact copper capability, spacing, dielectric test, inspection and material availability are confirmed per quotation rather than assumed from a generic capability statement.
FAQ
What is the most important AC-DC converter PCB layout rule?
Define the safety boundary and identify high-di/dt loops, high-dv/dt nodes, quiet sensing paths and heat paths before detailed placement. A single “short traces” rule cannot resolve the competing safety, EMI, thermal and control requirements.
How much creepage and clearance does a mains PCB need?
There is no universal value. Clearance depends on required impulse voltage, pollution degree, field conditions and altitude; creepage depends on working voltage, pollution degree, insulation grade and material group. Use the applicable end-equipment standard and document the assumptions.
Does an AC-DC power supply always need PFC?
No. The need depends on input power, equipment class, market and applicable harmonic-current rules. Even when active PFC is not mandatory, input-current waveform, inrush, conducted EMI and system power quality still require evaluation.
Is heavy copper always better for an AC-DC converter PCB?
No. It can reduce resistance and spread heat, but it changes manufacturability, spacing, vias, soldering and cost. Select copper from RMS/peak current, allowed temperature rise, geometry, thermal path and fabrication capability—not from current alone.
Conclusion
An AC-DC converter PCB should be released as a verified energy and insulation system, not as a schematic transferred to copper. Send HILPCB the electrical specification, safety assumptions, stackup, power-loop constraints, thermal data, production files and test plan so the quotation can address the construction that the product will actually qualify.