With the explosive growth of generative AI, LLM, and HPC, AI servers have become the core engine of data centers. Inside these servers, data throughput between accelerators like GPU and TPU has reached unprecedented TB/s levels, all relying on a well-designed and precisely manufactured Backplane or Motherboard PCB. Therefore, AI server motherboard PCB routing is no longer a simple electrical connection but has evolved into a complex engineering science integrating high-speed SI, PI, thermal management, and advanced manufacturing processes. This article will deeply analyze the key technologies and practical strategies for mastering this challenge from the perspective of a server power and cooling system engineer.
As an engineer focused on high-power density solutions, I know the profound impact of every design decision on system performance and reliability. From the layout of 48V VRM to the distribution of thousands of amperes of current, to signal transmission of PCIe 6.0 up to 64 GT/s, every detail of the AI server backplane PCB must be rigorously considered. A successful AI server motherboard PCB routing project requires not only meeting electrical performance but also balancing heat dissipation, manufacturability, and long-term stability, especially in the harsh data-center AI server motherboard PCB environment. Highleap PCB Factory (HILPCB) has deep accumulation in this field and can provide customers with comprehensive support from prototype to mass production.
Why is Stackup Design the Cornerstone of Routing Success for AI Server Backplanes?
Before starting any routing work, a well-optimized AI server motherboard PCB stackup is the starting point for all performance. Stackup design determines signal impedance, crosstalk levels, power network quality, and EMI/EMC performance. For complex designs like AI servers often exceeding 20 layers, stackup planning is paramount.
First, the choice of AI server motherboard PCB materials is crucial. Traditional FR-4 materials have excessive loss in high-frequency bands (>10 GHz) and can no longer meet the needs of PCIe 5.0/6.0 or higher speeds. We must turn to Ultra-Low Loss or Extremely-Low Loss materials, such as Tachyon 100G, Megtron 6/7/8, etc. These materials have lower Dk and Df, effectively reducing signal attenuation and distortion during transmission.
Second, the Stackup structure must provide a clear, continuous return path for high-speed signals. Every high-speed differential pair needs an adjacent, complete reference ground plane (GND) or power plane (PWR). Discontinuous reference planes cause sudden impedance changes in the return path, resulting in severe reflection and EMI problems. In Stackup design, we carefully arrange signal layers and reference plane layers, usually adopting symmetrical Stripline or Microstrip structures of "signal-ground-signal" or "signal-ground-power-signal" to achieve optimal SI. For a complex High-Speed PCB, a reasonable Stackup is half the battle.
Finally, the layout of power and ground planes is critical for PI. In AI servers, the instantaneous current demand of GPU and CPU is enormous, and a low-impedance PDN is key to ensuring stable operation. By setting multiple thick copper power/ground planes in the Stackup and utilizing the capacitance effect between planes, PDN impedance can be effectively reduced, providing clean and stable power to the chips.
How to Address Signal Integrity Challenges Brought by PCIe 5.0/6.0 and CXL?
With the popularity of high-speed buses like PCIe 5.0 (32 GT/s), PCIe 6.0 (64 GT/s), and CXL (Compute Express Link), SI has become the most challenging part of AI server motherboard PCB routing. At such high speeds, the PCB trace itself acts like a complex RF component, where any tiny flaw can lead to data transmission failure.
1. Precise Impedance Control: The control accuracy requirement for differential impedance (usually 85Ω or 100Ω) is extremely high, typically requiring control within ±5%. This depends not only on trace width, spacing, and dielectric thickness but also closely on manufacturing processes like copper foil roughness and etching precision. In the design phase, we use professional field solver tools (such as Ansys SIwave, Cadence Sigrity) for precise modeling and simulation to determine optimal trace geometric parameters.
2. Crosstalk Suppression: High-density routing makes electromagnetic coupling between adjacent differential pairs inevitable. To suppress Crosstalk, we must ensure that the spacing between differential pairs is at least 3-5 times the trace width (3W-5W rule). Meanwhile, long-distance parallel routing should be avoided as much as possible, and ground planes should be used for effective isolation.
3. Loss Compensation: Signals attenuate during transmission due to dielectric loss and conductor loss. To ensure sufficient "eye diagram" opening at the receiving end, in addition to selecting low-loss AI server motherboard PCB materials, Pre-emphasis and Equalization need to be considered in routing. Also, traces should be as short and straight as possible, avoiding excessive Via usage and corners.
4. Via Optimization: Via is a major impedance discontinuity point in high-speed links. Unoptimized Via will generate huge reflections, seriously affecting signal quality. For high-speed signals, we must adopt impedance-controlled Via design and perform Back-Drilling on Via Stubs to eliminate resonance effects. A high-quality AI server motherboard PCB prototype is crucial for verifying these complex designs.
Core Points of High-Speed SI Design
- Impedance Control Priority: Ensuring consistent impedance of all high-speed differential pairs throughout the link is the primary task to reduce reflection.
- Return Path is King: Provide a clear, continuous, low-inductance return path for every signal line, avoiding crossing split reference planes.
- Strictly Control Crosstalk: Maintain sufficient trace spacing, utilize shielding ground lines, and optimize routing topology to minimize coupling.
- Optimize Transition Structures: Carefully design transition areas like Via and connector pads, reducing impedance discontinuity through Back-Drilling and optimizing pad sizes.
- Simulation-Driven Design: Conduct comprehensive SI simulation before and after routing to predict and solve potential problems, rather than relying on physical testing.
Power Distribution Network (PDN) Design Strategies Under High Power Density
The power consumption of AI servers has soared from a few kilowatts to tens of kilowatts, with a single GPU's peak power consumption reaching 1-2kW. Providing stable and clean power for these "power-hungry beasts", poses unprecedented challenges to PDN design.
1. 48V Power Architecture: To reduce I²R losses, data centers are shifting from traditional 12V architecture to 48V architecture. At the PCB level, this means we need to handle higher voltages and more complex power conversion topologies. VRM (Voltage Regulator Module) needs to be as close to the load (GPU/CPU) as possible to reduce distribution losses and parasitic inductance.
2. High Current Transmission Scheme: Traditional PCB traces are no longer capable of transmitting hundreds or even thousands of amperes of current. We must adopt Heavy Copper PCB, with copper thickness reaching 6oz or higher. On some critical paths, copper bars (Busbar) are even directly embedded or laminated on the PCB to achieve extremely low DC resistance.
3. PDN Impedance Target: An excellent PDN design must maintain extremely low impedance across a wide frequency band from DC to hundreds of MHz. This requires a carefully designed decoupling capacitor network. Large-capacity electrolytic capacitors or polymer capacitors are responsible for energy storage in the low-frequency band, while thousands of ceramic capacitors (MLCC) are distributed around the chips to suppress high-frequency noise.
4. IR Drop and Thermal Analysis: Under high current, even milliohm-level resistance can cause significant voltage drop and heat generation. We must use professional PI simulation tools for detailed IR Drop and thermal analysis to ensure that the voltage at each power pin is within specifications and that hotspot temperatures on the PCB are controllable. This is crucial for the long-term stable operation of data-center AI server motherboard PCB.
Application and Optimization of Advanced Via Structures in AI Server Backplanes
In high-density, high-performance designs like AI server PCB, Via is not just a channel connecting different layers but a key factor affecting SI and PI. Traditional Through-hole Via is difficult to meet the needs, making advanced Via structures an inevitable choice.
1. Back-Drilling: As mentioned earlier, high-speed signal Via Stubs act like antennas generating resonance, severely destroying signals. Back-Drilling is a process of drilling out excess copper pillars of the Via from the back of the PCB, effectively eliminating the Stub effect. For PCIe 5.0 and above signals, Back-Drilling is almost a standard operation.
2. HDI Technology: To accommodate more functions in limited space, AI server motherboards widely adopt HDI technology. By using laser-drilled Microvias, Blind Vias, and Burried Vias, higher routing density can be achieved, signal paths shortened, and better Fan-out schemes provided for high-density packaging devices like BGA.
3. Power Integrity of Vias: For high-current paths, the current-carrying capacity and parasitic inductance of a single Via may become a bottleneck. Therefore, we usually use Via Array to share current and reduce equivalent resistance and inductance. Meanwhile, when designing power/ground Vias, it is necessary to ensure a solid connection with the power/ground planes to avoid forming hotspots.4. Connector Via Optimization: The backplane connector (such as PCIe CEM, OAM Mezzanine) area is a critical zone for signal integrity. The Via density here is extremely high, making optimization difficult. We need to precisely design the dimensions of the Pad and Anti-pad for each Via to match the target impedance and reduce crosstalk between Vias. As an experienced manufacturer, HILPCB can precisely control the manufacturing tolerances of these complex structures.
Performance Comparison of Different PCB Materials in High-Speed Applications
| Material Grade | Typical Material | Dk (@10GHz) | Df (@10GHz) | Applicable Speed |
|---|---|---|---|---|
| Standard FR-4 | S1141, IT-180A | ~4.2 | ~0.020 | < 5 Gbps |
| Mid Loss | FR408HR, TU-872SLK | ~3.6 | ~0.010 | 5-10 Gbps |
| Low Loss | I-Speed, M4S | ~3.4 | ~0.005 | 10-28 Gbps (PCIe 4.0/5.0) |
| Ultra Low Loss | Megtron 6, Tachyon 100G | ~3.0 | < 0.002 | > 28 Gbps (PCIe 6.0, 112G PAM4) |
Thermal Management and Heat Dissipation Design of AI Server PCB
Power consumption equals heat. An AI server chassis with 20kW power consumption is a massive heat source, and the PCB itself is a key link in heat generation and conduction. Effective thermal management is the prerequisite for ensuring stable server operation and avoiding throttling or downtime due to overheating.
1. Identify Heat Sources: During the PCB design phase, we need to precisely identify the main heat-generating components, such as MOSFETs and inductors in the VRM, high-speed transceivers (SerDes), and networking chips. Through thermal simulation, the temperature distribution in these areas can be predicted.
2. Optimize Thermal Paths: The PCB itself is part of the heat dissipation path. We place a large number of Thermal Vias to conduct heat from the bottom of components quickly to the inner ground or power planes. These large copper planes act like heat sinks, helping to spread heat evenly. This is particularly important for large-sized boards like server backplane PCB.
3. Integrate with System-Level Cooling: The thermal design of the PCB must be closely integrated with the cooling solution of the entire server (air cooling or liquid cooling). For example, in air-cooled systems, we place high-heat components in optimal positions within the airflow path. In liquid-cooled systems, the PCB may need to reserve mounting areas and contact interfaces for the Cold Plate to ensure heat is efficiently transferred to the coolant.
4. Thermal Properties of Materials: The Thermal Conductivity of PCB materials also affects heat dissipation efficiency. Although most epoxy resin substrates have low thermal conductivity, we can improve the overall equivalent thermal conductivity by increasing the copper content (such as using thick copper).
From Prototype to Mass Production: The Critical Role of DFM in AI Server PCB
A design that performs perfectly in simulation is a failure if it cannot be manufactured economically and reliably. Design for Manufacturability (DFM) is the key bridge turning design blueprints into reality, especially when dealing with complex AI server motherboard PCB routing.
The core of DFM is communicating with the PCB manufacturer (such as HILPCB) early in the design phase to understand their process capabilities and limitations. This includes:
- Minimum Trace Width/Spacing: AI server PCBs often require 3/3mil (0.075mm) or even finer trace width and spacing, which demands top-tier etching and photolithography capabilities.
- Drilling Accuracy and Aspect Ratio: Plating of deep holes (Aspect Ratio > 15:1) is a manufacturing challenge. We need to ensure that the Via design is within the manufacturer's capabilities.
- Lamination and Alignment: For boards with more than 20 layers, the alignment accuracy between layers is crucial. Any slight deviation can lead to open circuits or short circuits.
- Material and Warpage: AI server motherboards are huge in size and prone to warpage during high-temperature processes like Reflow. Through reasonable Stackup design (symmetrical structure) and panelization schemes, the risk of warpage can be minimized.
Whether for AI server motherboard PCB prototype used for functional verification, or AI server motherboard PCB low volume production to meet small-batch, customized needs, DFM is the cornerstone of product quality and yield. Highleap PCB Factory (HILPCB) provides free DFM analysis services to help customers identify and correct potential manufacturing risks before production, thereby saving valuable time and costs. We also excel at handling the smooth transition from prototype to mass production, ensuring consistency across different batches.
HILPCB AI Server PCB Manufacturing Capabilities Overview
| Max Layer Count | 64 Layers |
| Max Board Thickness | 12.0 mm |
| Min Trace Width/Spacing | 2.5/2.5 mil |
| Max Aspect Ratio | 20:1 |
| Impedance Control Accuracy | ±5% |
| Supported Materials | Megtron 6/7/8, Tachyon 100G, Rogers, etc. |
Ensuring Long-Term Reliability: Key Steps in Testing and VerificationFor AI servers deployed in data centers, reliability is the lifeline. Any failure can lead to huge economic losses. Therefore, strict testing and verification is the final and most important link in the AI server motherboard PCB routing process.
1. Electrical Testing: 100% flying probe or fixture testing is mandatory to check for opens and shorts. But for AI server PCB, this is far from enough.
2. Impedance Testing (TDR): We use Time Domain Reflectometry (TDR) to sample or fully inspect critical high-speed traces on the board to verify if their characteristic impedance meets design requirements. This is a direct physical measurement method to ensure signal integrity.
3. Reliability Testing: Sample boards need to pass a series of rigorous environmental and mechanical stress tests, such as Thermal Cycling, Thermal Shock, and SMT Simulation, to ensure long-term stable operation in the 24/7 operating environment of data centers. This follows the industry's highest standards such as IPC-6012 Class 3/3A.
4. Post-Assembly Testing: After completing prototype assembly, X-ray inspection is also required to check the quality of solder joints under packages such as BGA. Functional Test is the ultimate means to verify whether the entire board works as expected.
Conclusion: Systematic Engineering Thinking is the Key to Success
In summary, AI server motherboard PCB routing is an extremely complex system engineering project that requires designers and manufacturers to possess comprehensive cross-domain knowledge. From selecting suitable AI server motherboard PCB materials and building an optimized AI server motherboard PCB stackup, to finely handling SI issues of high-speed signals, robustly designing high-current PDN networks, and balancing thermal management and manufacturability, every link is closely connected and indispensable.
Mastering these challenges requires deep technical expertise, advanced simulation tools, top-tier manufacturing processes, and seamless collaboration between design and manufacturing. For data-center AI server motherboard PCB projects pursuing ultimate performance, choosing an experienced and technically leading partner like HILPCB is crucial. We can not only provide high-quality PCB manufacturing but also participate in your design process with engineering thinking, providing you with a one-stop solution from prototype to mass production, jointly creating the core hardware driving the future AI era.