Hello and welcome to HILPCB’s Stackup & Materials Academy. I’ll be your instructor today as we dive into a topic no engineer can avoid: rf pcb material comparison. This is not only about RF design. The underlying principles—how to read Dk/Df, how to balance cost vs. performance, and how to keep a design manufacturable—are the foundation of all high-speed and high-frequency PCB design.
Many engineers feel overwhelmed at the start of a project when faced with dozens of material options. Do you stay with familiar FR-4, or invest in expensive Rogers? How much does the difference between Dk 3.2 and 3.66 matter for a 28Gbps signal? In this lesson we will turn abstract parameters into practical stackup planning steps and decision logic you can use immediately. Through a complete pcb stackup tutorial, we will cover the full path from inputs to final manufacturing deliverables—helping your team build a standardized, validated stackup knowledge base.
The starting point of stackup design: define inputs and outputs
A professional stackup design is not guesswork. It is a rigorous engineering process that starts with clear inputs and ends with deliverable manufacturing documentation.
Design inputs: the “requirements spec” for stackup planning
Before opening your EDA tool, make sure you collect the following key information:
Signal Integrity (SI) requirements:
- Max signal data rate: Is it 1Gbps Ethernet or 56Gbps PAM4? Data rate determines how much loss (Df) you can tolerate.
- Impedance control: List all controlled impedance nets, e.g., 50Ω single-ended and 90Ω/100Ω differential. This is the most basic objective of stackup design.
- Crosstalk and timing: Spacing rules and routing-layer choices depend on the isolation the stackup provides.
Power Integrity (PI) requirements:
- Maximum operating current: Determines copper thickness for power/ground layers, e.g., 1 oz (35µm) standard vs. 2 oz (70µm) for higher current.
- Core voltages and rails: Complex FPGA/CPU designs may require multiple independent power layers.
Thermal management and reliability:
- Power dissipation of key devices: Placement and cooling needs for high-power devices (>20W) affect choices like thermal conductivity (Tc) and Tg.
- Operating environment: Automotive/industrial applications require higher thermal robustness; Tg > 170°C is a common baseline.
Safety and mechanical constraints:
- Operating voltage: High-voltage designs (>300V) impose CTI requirements, often CTI ≥ 600V.
- Final board thickness: e.g., 1.6mm ±10%—the combined constraint of all material thicknesses.
- Layer-count constraints: driven by cost, BGA pitch, and routing density.
Design outputs: a clear “construction drawing”
The final output of stackup design is a detailed manufacturing file set that tells the factory how to “build” your PCB. It typically includes:
- Lamination/stackup drawing: layer type (signal/ground/power), material models (e.g., IT-180A Core / 1080 PP), dielectric thickness, copper thickness.
- Impedance specification table: parameters for all controlled impedance traces (width/space/layer/reference/target impedance).
- Final thickness and tolerance.
- Special manufacturing requirements: e.g., backdrill depth, Via-in-Pad filling, etc.
Quick reference for material parameters: from FR-4 to RF materials
To do rf pcb material comparison well, you must understand the key parameters. Dk (dielectric constant) affects signal velocity and impedance; Df (dissipation factor) determines attenuation. Tg/Td represent thermal robustness; CTI relates to electrical safety.
Comparison table of mainstream PCB material parameters
The table below compares commonly used materials from standard FR-4 to high-speed/RF options. Note that Dk and Df vary with frequency; these reference values are suitable for initial selection.
| Material class | Common models | Dk (@10GHz) | Df (@10GHz) | Tg (°C) | Td (°C) | CTI (V) | Glass weave | Typical applications |
|---|---|---|---|---|---|---|---|---|
| Standard FR-4 | Shengyi S1141 | ~4.2 | ~0.020 | 140 | 315 | >175 | 7628, 1080 | Low-speed digital, power |
| Mid-Tg FR-4 | ITEQ IT-158 | ~4.0 | ~0.016 | 150 | 330 | >175 | 7628, 1080 | Multilayer, consumer electronics |
| High-Tg FR-4 | ITEQ IT-180A | ~3.9 | ~0.012 | 180 | 345 | >175 | 7628, 1080 | Servers, automotive, lead-free process |
| Mid loss | Panasonic Megtron 4 | ~3.6 | ~0.004 | 185 | 380 | >175 | Spread Glass | 10-28Gbps high-speed backplanes |
| Low loss | ITEQ I-Speed | ~3.4 | ~0.005 | 200 | 360 | >175 | Spread Glass | 28-56Gbps data center |
| Very low loss | Panasonic Megtron 6 | ~3.2 | ~0.002 | 210 | 410 | >175 | Spread Glass | 56Gbps+ high-end servers |
| RF/microwave | Rogers RO4350B | 3.66 | 0.0037 | 280 (TM) | 390 | >175 | Woven Glass | Antennas, PA, radar |
How to read the parameters:
- Dk (Dielectric Constant): Lower Dk means faster propagation; for the same impedance, it enables wider traces (better manufacturability).
- Df (Dissipation Factor): Lower Df means less energy loss—critical for long, high-frequency links. This is the core focus of
low loss laminate tutorial. - Tg (Glass Transition Temp): Temperature where the resin transitions from glassy to rubbery. Higher Tg reduces deformation risk during lead-free reflow (~260°C).
- Td (Decomposition Temp): Temperature at which the material loses 5% mass due to decomposition; a key indicator of long-term thermal stability.
- Glass weave: Standard weave (e.g., 1080) can cause Dk non-uniformity and “glass weave effect” (skew) on high-speed differential pairs. Spread Glass mitigates this.
Core stackup paradigms: classic structures from 4 to 10 layers
A good stackup protects signal quality. Below are mass-production-proven paradigms you can use as a starting point.
Stackup examples and typical use
| Layer count | Classic structure (Top -> Bottom) | Pros | Cons | Typical applications |
|---|---|---|---|---|
| 4-layer | SIG - GND - PWR - SIG | Lowest cost, simple | Poor EMI; unstable impedance | IoT modules, simple controllers |
| 6-layer | SIG - GND - SIG - PWR - GND - SIG | Good references; improved EMI | Higher cost; routing still limited | Consumer boards with high-speed I/O (e.g., USB 3.0) |
| 8-layer | SIG - GND - SIG - PWR - GND - SIG - GND - SIG | Excellent EMI/SI; tight coupling to reference planes | Higher cost; tighter lamination process window | Servers, switches, ideal for hdmi pcb stackup guide |
| 10-layer | SIG - GND - SIG - GND - PWR - PWR - GND - SIG - GND - SIG | More routing layers and power isolation | Higher cost; longer lead time | High-density compute cards, complex comms |
Deep dive: a classic 8 layer stackup example
Let’s use the most common 8-layer design as an example:
- L1 (Top) / L8 (Bottom): typically for components and short routing.
- L2 / L7 (Inner GND): adjacent to outer signal layers for the shortest return path; helps suppress EMI radiation.
- L3 / L6 (Inner SIG): ideal for high-speed signals (e.g., differential pairs). Sandwiched between ground/power planes, forming a natural stripline structure with excellent shielding.
- L4 (PWR) / L5 (GND): core power and ground planes. Placing them adjacent creates large plane capacitance to support a low-impedance PDN.
This symmetric, clearly partitioned structure supports electrical performance and is also the basis for good pcb warpage control.
Golden rules of stackup design: signal, power, ground, and copper thickness
Planning steps and principles
Prioritize complete reference planes: The adjacent layer of any high-speed signal layer should be a solid GND plane. This is the #1 rule for crosstalk control and impedance continuity. Avoid large plane splits.
Tight coupling between signal and reference: Reducing dielectric thickness (e.g., using 1080 or 2116 Prepreg) improves coupling, reduces crosstalk, and suppresses radiation.
Symmetry: The stackup must be strictly symmetric around the center (materials, thickness, copper). If L1 is 1 oz copper, L8 should also be 1 oz. Asymmetry is a common cause of warpage during reflow.
Copper thickness selection:
- Inner-layer signals: typically 0.5 oz (18µm) for finer geometry and better impedance control.
- Outer signal/power: typically 1 oz (35µm) for a balance of current and routing.
- High-current planes: for >5A, consider 2 oz (70µm) or thicker, but note thick copper increases etch difficulty and cost.
Pay attention to Prepreg resin content (
prepreg resin content lesson): Prepreg melts during lamination and fills copper patterns on the Core. High Resin Content (RC) PP (e.g., 1080 RC 65%) fills better but has larger thickness variation; low RC PP (e.g., 7628 RC 45%) is more stable. For impedance, use the post-lamination thickness, not the raw thickness. HILPCB engineers can recommend the best PP models based on routing density.
Hybrid stackups and special materials: meeting extreme performance requirements
When a single material can’t satisfy all requirements, Hybrid Stackup and special materials become necessary.
Common hybrid stackup options
| Hybrid option | Structure example | Benefits | Challenges and notes |
|---|---|---|---|
| Rogers + FR-4 | L1/L2 use Rogers RO4350B; inner layers use IT-180A | Preserve RF performance while reducing cost | CTE mismatch requires special lamination; Rogers + FR-4 Prepreg bonding often needs Plasma treatment to improve adhesion. |
| High-speed material + FR-4 | L3/L6 high-speed layers use Megtron 6; other layers use IT-180A | Use expensive materials only where needed | Different materials have different lamination windows (temperature/pressure); requires tight factory process control. |
Special substrate overview
- MCPCB: An ultra-thin dielectric bonds copper foil to a thick aluminum core. Thermal performance is orders of magnitude better than FR-4, ideal for high-power LED and power module heat spreading.
- FPC / Rigid-Flex: Polyimide-based for 3D routing and dynamic bending. Stackup design must focus on copper type in bend areas (rolled annealed better than ED copper) and Stiffener design.
Manufacturing impact: the “last mile” from design to physical boards
A perfect stackup that cannot be built consistently is still a failed design. Below are key manufacturing considerations.
HILPCB manufacturing capability and design recommendations
Resin Flow: During the
press cycle, resin in Prepreg flows. If inner-layer copper coverage is too low (large voided areas), resin over-fills and the effective dielectric thickness becomes much smaller than designed—causing impedance drift. HILPCB recommends inner-layer copper coverage ≥ 70%.Warpage control (
pcb warpage control): Beyond symmetric stackup, in-layer copper uniformity matters. Avoid heavy copper on one side of the board while the other side has almost none. Our CAM engineers run copper balance checks before production and will propose optimizations.Back-drilling: For signals above 10Gbps, unused Via barrel (Stub) can resonate like an antenna and damage signal quality. Back-drilling removes the unused stub from the PCB backside. In design, specify which vias are backdrilled, target layers, and maximum remaining stub length (e.g., <10mil).
Impedance Coupon: We add one or more impedance coupons with the same structure and parameters on the production panel. Each shipment includes a TDR impedance report to ensure 100% compliance with your impedance requirements.
HILPCB: your dedicated stackup and materials advisor
The purpose of learning is solving real problems. At HILPCB, we are not only a manufacturer—we are a partner in your design process.
200+ in-stock materials: We stock 200+ material options from standard S1141 FR-4 to Rogers and Megtron series, plus a wide range of Core and Prepreg thicknesses—so your project won’t stall due to procurement delays.
Professional impedance lab: We use industry-leading Polar Instruments impedance test equipment to validate every controlled-impedance build.
Fast stackup proposal service: Struggling with complex stackup design and impedance calculation? HILPCB provides a free stackup proposal service—share your basic requirements and our senior engineers will tailor a solution.
Get a free stackup proposal now
Submit your requirements (layer count, thickness, signal data rate, target impedance). Within 24 hours, HILPCB engineers will provide a professional stackup recommendation validated by DFM and impedance calculation.
Claim my stackup proposalThat concludes today’s lesson. I hope this comprehensive rf pcb material comparison and stackup walkthrough helps you better understand how to select materials and plan a reliable stackup. Remember: a great stackup is the foundation of high-performance products and the bridge between design and manufacturing.
Internal links:
Conclusion
This article uses rf pcb material comparison to explain material parameters, stackup planning, impedance/thermal/cost trade-offs, and manufacturing considerations, with tables and examples to help teams build a standard stackup library and manage risks across design, materials, and test. By following the checks and process window—and involving HILPCB’s DFM/DFA team early—you can accelerate prototype and volume delivery while maintaining quality and compliance.
For manufacturing and assembly support, contact HILPCB Turnkey Assembly or SMT Assembly for DFM/DFT recommendations.
Common Questions
Which parameter should come first when selecting an RF PCB material?
Start with the target frequency band and the allowable loss budget, then look at Dk, Df, Tg, CTE, and material availability. The key is not chasing one perfect number but finding a material set that still works across performance, manufacturability, reliability, and cost.
Why are hybrid stackups so common in RF and high-speed projects?
Because not every layer needs premium low-loss laminate. Using advanced material only on the critical RF or high-speed layers, while keeping the rest on mature FR-4 or high-Tg material, is often the most practical balance between signal performance and total cost.
Why is stackup symmetry so important?
Symmetry helps not only electrical balance but also mechanical stability. An unbalanced stackup is more likely to warp during lamination or reflow, and many assembly headaches that look like process issues actually begin with an uneven layer build.
Why should the manufacturer be involved early in stackup planning?
Because resin flow, lamination feasibility, impedance coupon strategy, and backdrill capability cannot be judged from CAD alone. Early manufacturing input prevents the common situation where the simulation looks good but the production window is too narrow.