A 5G NSA PCB is a telecom printed circuit board designed for non-standalone 5G equipment, where 5G NR works with existing LTE/EPC infrastructure through LTE-NR dual connectivity. For board-level review, the important question is not only whether the product is "5G"; it is which NSA function the board supports, which RF and high-speed interfaces it carries, and which manufacturing controls are needed before release.
This guide is written for RF engineers, hardware teams, sourcing engineers, and product owners reviewing 5G radio, small-cell, DU, BBU-like, or Cloud RAN hardware before prototype or volume quotation.
Key Takeaways
- 5G NSA hardware must support 5G NR while remaining compatible with LTE/EPC-based deployment assumptions, so the PCB often carries both RF coexistence and high-speed transport risk.
- EN-DC, RF front-end density, massive MIMO, fronthaul/backhaul interfaces, and outdoor thermal loading all affect the board stackup, material choice, via strategy, and test plan.
- Sub-6 GHz RF sections, mmWave antenna modules, DU/baseband boards, and Cloud RAN accelerator cards should not be reviewed as one generic "5G PCB."
- Low-loss laminate selection is only one part of the decision. Impedance control, dielectric stability, copper roughness, via stubs, connector launches, PDN design, thermal paths, and DFM limits must be reviewed together.
- A strong RFQ package should include stackup intent, target impedance, RF band or frequency range, insertion-loss expectations, thermal load assumptions, test coupons, acceptance criteria, and assembly constraints.
Table of Contents
- What is a 5G NSA PCB?
- How NSA architecture changes the PCB review
- Which 5G NSA board type are you designing?
- How to choose materials for 5G RF and high-speed sections
- RF layout, impedance and antenna-feed control
- High-speed digital SI and PI on DU, BBU and Cloud RAN boards
- Thermal design for PA, FPGA, ASIC and small-cell hardware
- Massive MIMO and antenna-array PCB risks
- Common failure modes in 5G NSA PCB builds
- Cost drivers and design trade-offs
- RFQ checklist for 5G NSA PCBs
- Why work with HILPCB for 5G NSA PCB manufacturing
- Reference standards and specifications
- FAQ
- Next steps
What is a 5G NSA PCB?
A 5G NSA PCB is a board used in non-standalone 5G network equipment, where 5G NR is introduced while LTE and EPC infrastructure still provide part of the system anchor. In 3GPP terminology, the common deployment path is associated with E-UTRA-NR Dual Connectivity, often discussed as EN-DC or NSA Option 3.
At board level, that architecture creates a practical difference from a simple "5G high-frequency board" label. The hardware may need to handle LTE coexistence, NR RF paths, synchronization, baseband processing, high-speed fronthaul, power amplifier heat, outdoor reliability, and dense mechanical packaging at the same time.
A 5G NSA PCB can therefore mean several different things:
- a 5G RF PCB inside a radio unit or active antenna unit
- a 5G DU PCB carrying baseband processing and fronthaul interfaces
- a 5G small cell PCB that combines RF, compute, timing, Ethernet, power and enclosure constraints
- a BBU-like board used in integrated or transitional RAN equipment
- a Cloud RAN PCB or accelerator card used in virtualized baseband infrastructure
Those boards do not share the same risk profile. An RF front-end board is dominated by loss, isolation, phase consistency and thermal density. A DU board is dominated by SerDes, power integrity, memory interfaces, timing, connector launches and thermal management. A small cell often has both problems at once, compressed into a small outdoor enclosure.
The right review starts by naming the board function before naming the laminate.
How NSA architecture changes the PCB review
NSA architecture is useful because operators can introduce 5G NR without replacing the entire LTE/EPC network at once. For PCB teams, however, that transitional architecture usually adds complexity rather than removing it.
The first issue is coexistence. LTE and NR functions can exist in the same product family, enclosure, or even board system. That raises the burden on RF isolation, harmonic control, shielding, grounding, filtering and power-noise containment. A PCB that works well as a single-band RF design can fail when additional bands, duplexers, power amplifiers and digital interfaces are added nearby.
The second issue is throughput concentration. A 5G DU PCB or baseband board has to move high-rate data between compute silicon, memory, timing devices, Ethernet/fronthaul interfaces, optical modules and RF-related processing blocks. The limiting factor may shift from RF material to connector launch design, via stubs, reference-plane continuity, crosstalk, or PDN impedance.
The third issue is thermal density. Power amplifiers, GaN devices, FPGAs, ASICs, high-speed retimers, optical cages and DC-DC converters can sit close together. In outdoor small cells and radio units, airflow is often limited. The PCB becomes part of the thermal path rather than a passive carrier.
The fourth issue is validation scope. A board can pass continuity and impedance tests while still failing RF sensitivity, EVM, phase consistency, thermal cycling, or production repeatability. For NSA hardware, the release plan should link PCB fabrication controls to the system-level tests the customer will run later.
| NSA board-level review item | What to confirm | Why it matters |
|---|---|---|
| Architecture scope | EN-DC / NSA function, RF path, DU/baseband role, or Cloud RAN role | Prevents one generic "5G PCB" quote from hiding different technical risks |
| RF band and frequency range | Sub-6 GHz, mmWave module, LTE coexistence, or mixed RF path | Drives material loss, stackup, antenna feed and test-coupon requirements |
| High-speed interfaces | Ethernet, fronthaul, PCIe, memory, SerDes, optical module lanes | Determines via strategy, back-drilling, insertion-loss budget and connector launch controls |
| Thermal sources | PA, FPGA, ASIC, optical module, power stage, enclosure conduction path | Defines copper weight, thermal-via arrays, heat spreaders, metal base or mechanical interface |
| Manufacturing acceptance | Impedance, insertion loss, coupon design, flatness, registration and inspection | Converts design goals into measurable fabrication controls |
Which 5G NSA board type are you designing?
The most common mistake in telecom PCB sourcing is asking for a "5G NSA PCB" without saying which equipment layer the board belongs to. That phrase is too broad for material selection or DFM review.
Use the table below as an early classification gate.
| Board type | Typical function | Main PCB risk | Likely manufacturing focus |
|---|---|---|---|
| 5G RF PCB | RF transceiver, PA chain, filters, couplers, LNAs, antenna feed | Insertion loss, impedance, isolation, phase consistency, heat near RF path | Low-loss laminate, hybrid stackup, RF launch control, VNA coupon planning |
| AAU / massive MIMO board | Antenna feed network, RF channel distribution, beamforming support | Channel-to-channel consistency and thermal density | Dk uniformity, tight registration, repeatable copper geometry, thermal via design |
| 5G DU PCB | Baseband processing, fronthaul, timing, synchronization, Ethernet/optical links | High-speed digital SI/PI and heat from processors | HDI, back-drilling, high-speed laminate, controlled impedance, PDN stackup |
| 5G small cell PCB | Compact radio + compute + power in one enclosure | RF, thermal, power and mechanical constraints collide | Dense HDI, shield design, thermal conduction, DFM/DFT and assembly process control |
| BBU-like PCB | Transitional or integrated baseband equipment | High layer count, connectors, timing, memory and fabric interfaces | Multilayer stackup, press-fit or high-speed connectors, back-drilled vias |
| Cloud RAN PCB / accelerator card | Virtualized baseband in server or edge infrastructure | Server-class high-speed I/O and power delivery | High-speed PCB, PCIe-class routing, thermal/mechanical fit, connector reliability |
A procurement engineer looking for a small-cell PCB needs different quote inputs from a team building an RF front-end board. A DU board review should not be dominated by antenna-feed language. A mmWave antenna module should not be quoted like a normal high-speed server board.
How to choose materials for 5G RF and high-speed sections
Material selection for 5G NSA hardware should start with the signal class, not the brand name. Low-loss laminates such as Rogers, PTFE-based materials and other RF substrates can be appropriate for RF paths, but they are not automatically required for every layer of every board.
A practical review separates three zones:
- RF zone โ transmission lines, couplers, filters, antenna feed networks, launch transitions and sensitive RF routing.
- High-speed digital zone โ SerDes lanes, Ethernet/fronthaul interfaces, memory interfaces, FPGA/ASIC breakouts and optical-module lanes.
- Power and control zone โ DC-DC stages, bias networks, low-speed controls, monitoring circuits and housekeeping functions.
A hybrid stackup is often more realistic than making the whole PCB from the most expensive RF laminate. For example, the RF layers may use a low-loss material while other layers use a more cost-effective high-speed or FR-4-class material, provided the lamination process, CTE behavior, registration and drilling reliability are controlled.
The material choice should consider the following properties:
| Material parameter | Why it matters in 5G NSA PCB review | Practical review note |
|---|---|---|
| Dk stability | Affects impedance, phase delay and RF feed-network consistency | Look at frequency, temperature and lot-to-lot expectations, not only nominal Dk |
| Df / loss tangent | Drives insertion loss in RF and high-speed channels | More important as trace length, frequency and modulation sensitivity increase |
| Copper roughness | Increases conductor loss at high frequency | Low-profile copper may be important for RF or high-speed insertion loss |
| Z-axis CTE | Affects plated-through-hole reliability through thermal cycling | Important for outdoor radios, thick boards and hybrid laminates |
| Thermal conductivity | Helps local heat spreading but rarely solves PA heat alone | Review with copper planes, vias, coins, chassis and enclosure path |
| Process compatibility | Determines drilling, plating, lamination and dimensional stability | Hybrid stackups need early supplier review |
FR-4 is not automatically wrong. It is wrong when the required loss, impedance stability, phase consistency, thermal exposure or high-speed channel budget exceeds what that stackup can safely support. Conversely, using a premium laminate everywhere can inflate cost without fixing via discontinuities, poor grounding, bad antenna clearance or weak thermal paths.
HILPCB commonly reviews 5G NSA PCB material decisions alongside Rogers PCB, high frequency PCB, high-speed PCB and hybrid-stackup options, so the quote reflects the actual electrical zones instead of a one-material assumption.
RF layout, impedance and antenna-feed control
A 5G RF PCB fails when the electromagnetic design and fabrication process are not treated as one system. The CAD layout may show a nominal 50-ohm feed, but the shipped board only behaves as intended if the dielectric thickness, copper geometry, copper roughness, plating, solder mask effect, surface finish, connector launch and reference-plane continuity are all controlled.
The antenna or RF launch area should be reviewed first. Many field problems begin with a small violation near the antenna: copper pour too close to the keep-out zone, a screw boss near the radiator, a shield wall that detunes the feed, or a cable/connector transition that was not included in simulation. In a compact small cell, these errors can be more damaging than the laminate choice.
A disciplined RF layout review checks:
- 50-ohm or differential RF transmission-line geometry based on the actual stackup
- clean reference-plane continuity under RF routes
- controlled transitions through vias, connectors and launch structures
- adequate clearance around antennas and keep-out regions
- isolation between PA outputs, LNA inputs, clocks, switching converters and digital buses
- shielding strategy that does not accidentally degrade antenna performance
- test coupons that represent the actual RF trace geometry and via transitions
For antenna arrays and beamforming paths, length matching alone is not enough. Phase consistency also depends on Dk uniformity, copper geometry repeatability, etching tolerance, layer registration and how consistently each feed path transitions through the board.
| RF design area | Common risk | PCB control |
|---|---|---|
| Antenna keep-out | Detuned radiation pattern and reduced range | Mechanical keep-out review, copper clearance and enclosure coordination |
| RF trace geometry | Impedance mismatch and return loss | Controlled stackup, impedance modeling and production coupons |
| Connector launch | Reflections and inconsistent S-parameters | Launch simulation, ground via fence review and VNA validation |
| PA-to-LNA isolation | Desensitization and spurious coupling | Physical separation, shielding, grounding and filter placement |
| Beamforming feed network | Phase error between channels | Dk uniformity, length/phase control and repeatable routing geometry |
| Switching power nearby | Conducted or radiated noise into RF path | Power-stage partitioning, filter placement and return-current control |
High-speed digital SI and PI on DU, BBU and Cloud RAN boards
A 5G DU PCB or Cloud RAN PCB is often closer to a high-performance server or networking board than a traditional RF board. It may include FPGAs, ASICs, DDR memory, retimers, Ethernet PHYs, optical-module cages, timing devices, PCIe-class interfaces and high-current voltage rails.
The biggest SI risk is usually not the straight section of a trace. It is the discontinuity: via stubs, BGA breakout, layer transition, connector launch, AC-coupling capacitor footprint, reference-plane split, or dense via field under a high-speed component.
Back-drilling, blind/buried vias and HDI fan-out are not prestige features. They are tools for removing avoidable discontinuities when the channel budget demands it. If the channel is short and slow enough, they may not be needed. If the channel is long, high-speed, or routed through thick multilayer boards, via-stub control can become central to the design.
Power integrity has the same practical logic. A processor or FPGA can fail in system tests even when every voltage rail measures correctly at DC. The PDN must support transient current demand across frequency, and the PCB stackup must provide short return paths, stable reference planes, decoupling access and thermal spreading.
DU / Cloud RAN SI and PI review checklist
| Area | What to review | Why it matters |
|---|---|---|
| Layer stackup | Signal-reference pairing, plane assignment and dielectric thickness | Sets impedance, return paths and crosstalk behavior |
| High-speed vias | Stub length, antipad size, back-drill depth and via-to-via spacing | Reduces reflections and mode conversion |
| BGA breakout | HDI need, escape routing, via-in-pad and manufacturability | Prevents density from forcing poor channel geometry |
| Connector launch | Footprint, ground transition, voids and launch modeling | Often dominates return loss at high speed |
| PDN | Target impedance, decoupling placement, plane spreading and rail isolation | Controls transient noise and jitter coupling |
| Timing | Clock routing, isolation and power filtering | Protects synchronization and phase-sensitive functions |
| Test strategy | TDR coupons, insertion-loss coupons, X-ray/AOI and functional tests | Converts design assumptions into measurable release controls |
For boards that combine RF and digital sections, SI/PI work also becomes an RF problem. A noisy power rail, clock spur or high-speed return path can degrade receiver sensitivity even when the RF trace itself is correctly designed.
Thermal design for PA, FPGA, ASIC and small-cell hardware
Thermal management is not a separate mechanical issue that happens after PCB layout. In 5G NSA equipment, thermal choices shape the board stackup, copper distribution, via arrays, component placement and enclosure interface.
The main heat sources are usually power amplifiers, GaN devices, FPGA/ASIC packages, high-current power stages, optical modules and dense memory regions. In outdoor small cells and radio units, the board may also face solar loading, sealed enclosures, limited airflow and wide ambient-temperature swings.
Common PCB-level thermal tools include:
- heavier copper planes for lateral heat spreading
- thermal via arrays under exposed pads and power packages
- filled and capped vias where assembly or void control requires it
- copper coins or embedded heat spreaders for severe local heat flux
- metal-core or metal-backed approaches for specific power modules
- chassis conduction paths coordinated with mechanical hardware
- component placement that separates RF sensitivity from hot power areas
Thermal vias are useful only when they connect to a real heat path. A dense via array under a hot package may still perform poorly if the backside plane is isolated, the copper area is too small, the interface material is weak, or the enclosure cannot remove the heat.
| Thermal method | Best use case | Watch-out |
|---|---|---|
| Heavy copper planes | Spreading heat and carrying current in power sections | Etching compensation, copper balance and lamination stress |
| Thermal via arrays | Moving heat from package pad to inner/backside copper | Via fill, solder wicking, voiding and real backside heat path |
| Copper coin / heat spreader | High local heat flux from PA, ASIC or power module | Mechanical tolerance, lamination complexity and assembly coplanarity |
| Metal-core PCB | Specific power or LED/power sections where a metal base is appropriate | Not a universal solution for RF/high-speed multilayer boards |
| Chassis conduction | Outdoor small cells and radio units | Requires mechanical, TIM and screw-torque coordination |
| Hybrid stackup | Combining RF loss control and cost control | Needs early lamination and CTE review |
HILPCB can review heavy copper PCB, high thermal PCB and metal core PCB routes where they match the actual thermal architecture. The important point is to choose the heat path deliberately instead of assuming a thicker board or premium laminate will solve thermal stress.
Massive MIMO and antenna-array PCB risks
Massive MIMO increases the importance of repeatability. A single RF channel can sometimes be tuned, debugged or calibrated in isolation. An antenna array needs many channels to behave consistently enough for beamforming and calibration to remain stable.
That consistency is affected by manufacturing details:
- dielectric constant uniformity across the panel
- etching tolerance on RF feed lines
- registration between layers
- solder mask openings near RF structures
- via placement and plating repeatability
- connector and cable-launch variation
- thermal gradients across the array
- mechanical flatness and assembly pressure
The feed network should be reviewed as a controlled manufacturing object, not only a schematic function. If different channels pass through different layer transitions or local copper environments, electrical length matching in CAD may not be enough. Layout symmetry, reference-plane discipline and process repeatability are part of the RF design.
For AAU and antenna-array work, ask three questions before release:
- Do all comparable RF channels see comparable dielectric, copper, via and launch environments?
- Are the acceptance coupons representative of the actual array-feed geometry?
- Has the thermal gradient across the array been considered as a phase and reliability issue, not only a component temperature issue?
Common failure modes in 5G NSA PCB builds
A useful 5G NSA PCB guide should tell the reader where projects usually fail. The table below is designed as a release-review asset for engineering and sourcing teams.
| Failure mode | Likely cause | Board-level symptom | Prevention / review action |
|---|---|---|---|
| RF range or sensitivity is worse than expected | Antenna keep-out violation, poor launch, PA noise coupling, impedance mismatch | Weak coverage, failed RF test, unstable throughput | Review antenna area, connector launch, RF grounding, shielding and RF coupons before build |
| Insertion loss exceeds budget | Wrong material assumption, copper roughness, long route, via transitions | Channel margin loss, high EVM or failed S-parameter test | Define material, trace length, via count, coupon and VNA acceptance early |
| Beamforming inconsistency | Dk variation, unequal feed environments, registration or etching variation | Channel calibration drift or poor array performance | Control Dk, geometry, symmetry, phase path and process repeatability |
| High-speed link instability | Via stubs, connector launch discontinuity, crosstalk, weak reference path | Bit errors, link training failure, intermittent resets | Use SI review, back-drilling/HDI where needed, and TDR/insertion-loss validation |
| FPGA/ASIC rail noise | Weak PDN, poor decoupling placement, plane splits | Jitter, functional instability, RF spurs | Review PDN impedance, decoupling loop inductance and return-current paths |
| Thermal throttling or drift | Incomplete heat path, weak via array, hot PA or optical module | Reduced output power, degraded reliability, timing drift | Model heat path, review copper/coin/chassis path and validate with thermal testing |
| Assembly yield loss | Dense BGA, RF shields, via-in-pad or uneven copper balance | Opens, shorts, voids, tombstoning, warpage | Add DFM/DFT review, X-ray plan, copper balance and assembly fixture planning |
| Outdoor reliability failure | Moisture, thermal cycling, vibration, CTE mismatch | Intermittent operation or cracked solder joints | Confirm material, surface finish, coating, enclosure, thermal cycle and mechanical stress plan |
| Cost escalation after quote | Board function not defined, overuse of premium laminate, late test requirements | Quote changes, long lead time, re-spin | Provide architecture, stackup intent, acceptance criteria and test needs in the first RFQ |
Cost drivers and design trade-offs
The cost of a 5G NSA PCB is driven less by the word "5G" and more by the controls required to make the board repeatable.
The main cost drivers are:
- low-loss or RF laminate selection
- hybrid lamination complexity
- layer count and board thickness
- HDI build-up layers, blind/buried vias and via-in-pad
- back-drilling tolerance and inspection
- heavy copper, copper coins or embedded heat spreaders
- tight impedance or phase-control requirements
- RF shields, fine-pitch BGAs and optical cages in assembly
- VNA, TDR, thermal, X-ray or functional testing requirements
- panel use and mechanical outline constraints
A good cost review does not simply remove premium features. It asks where each expensive feature reduces a real risk.
| Decision | Lower-cost direction | Higher-control direction | When to choose the higher-control path |
|---|---|---|---|
| Laminate | FR-4 or mid-loss high-speed material | Rogers/PTFE/RF laminate or hybrid stackup | RF loss, phase consistency or channel budget requires it |
| Via strategy | Through vias | Back-drilled, blind/buried or HDI vias | Stub or density risk threatens SI or routing feasibility |
| Copper | Standard copper weights | Heavy copper, thick copper or copper coin | Current density or heat flux cannot be handled by standard copper |
| Test plan | Electrical test and basic impedance coupons | TDR, VNA S-parameter coupons, X-ray and functional fixtures | RF/high-speed performance must be verified before assembly or shipment |
| Assembly | Standard SMT | Fine-pitch BGA, RF shield, optical cage and thermal-interface process control | Dense telecom modules need repeatable placement and inspection |
The most cost-effective board is usually not the simplest board. It is the board whose controls match the actual failure risks.
RFQ checklist for 5G NSA PCBs
A strong RFQ package helps the PCB supplier quote the board as a telecom engineering build rather than as a generic multilayer PCB.
Design files
- Gerber or ODB++/IPC-2581 fabrication data
- Drill files and drill table
- Netlist
- Assembly drawings, centroid file and BOM if PCBA is required
- Mechanical outline, enclosure constraints and keep-out notes
- Stackup drawing or target stackup intent
- Controlled-impedance table
- RF coupon or high-speed coupon requirements
- Surface finish requirement
- Solder mask color and legend requirement
- Test requirements and acceptance criteria
RF and high-speed parameters
- RF band or operating frequency range
- Sub-6 GHz, mmWave, antenna module, RF front-end or mixed-signal scope
- Target impedance values and tolerance
- Insertion-loss target, if defined
- Return-loss or S-parameter test requirement, if defined
- Differential pair speeds and protocols
- Maximum via-stub allowance or back-drilling requirement
- Connector type and launch constraints
- Critical nets requiring special handling
- Shielding or cavity requirements
Thermal and mechanical data
- Main heat sources and estimated power dissipation
- Junction-to-board or package thermal assumptions, if available
- Required copper weight by layer
- Thermal-via fill/cap requirements
- Copper coin or heat-spreader requirements
- Heat sink, chassis or TIM interface notes
- Operating ambient range
- Outdoor, vibration or thermal-cycling requirements
- Flatness or coplanarity requirements
Manufacturing and quality expectations
- Prototype quantity and target volume
- IPC class expectation
- Impedance coupon and measurement method
- VNA or S-parameter test requirement
- X-ray inspection requirement for BGA/via-in-pad
- AOI, electrical test and functional test scope
- Serialization or traceability requirement
- Required reports: impedance, microsection, COC, material certificate, test report
Commercial details
- Target lead time
- Expected annual volume
- Preferred material brand or approved alternates
- Budget sensitivity and acceptable alternate stackups
- Export, packaging and logistics requirements
- Whether bare PCB, turnkey PCBA or box-build support is required
The most useful RFQ statement is not "quote 5G NSA PCB." A stronger statement is: "Quote a 5G small-cell RF/baseband board with controlled 50-ohm RF traces, specified high-speed differential pairs, thermal-via arrays under PA and FPGA regions, and supplier review for hybrid low-loss stackup alternatives."
Why work with HILPCB for 5G NSA PCB manufacturing
A 5G NSA PCB supplier must understand both telecom board physics and production control. HILPCB supports the parts of the project where fabrication choices affect RF, high-speed and thermal behavior.
Relevant HILPCB support areas include:
- high frequency PCB manufacturing for RF and microwave designs
- Rogers PCB fabrication for low-loss and hybrid RF stackups
- high-speed PCB review for SerDes, connector and backplane-like channels
- HDI PCB capability for dense BGA breakout and compact telecom hardware
- heavy copper PCB and thermal-path review for PA, power and outdoor radio designs
- turnkey PCB assembly for RF shields, fine-pitch devices, optical modules and functional test planning
For 5G NSA projects, the strongest collaboration usually happens before the first prototype. Early supplier review can catch stackup conflicts, RF material overuse, via-stub risk, copper-balance problems, unrealistic test requests and assembly constraints before they become expensive re-spins.
Reference standards and specifications
These references are listed as plain-text standards and specifications for traceability. Final compliance and product performance must be verified at the system and equipment level.
- 3GPP TS 37.340 โ NR; Multi-connectivity; Overall description; Stage 2
- 3GPP TS 38.300 โ NR; NR and NG-RAN Overall description; Stage 2
- 3GPP TS 38.101-1 โ NR; User Equipment radio transmission and reception; FR1
- 3GPP TS 38.101-2 โ NR; User Equipment radio transmission and reception; FR2
- 3GPP TS 38.104 โ NR; Base Station radio transmission and reception
- ITU-R M.2410 โ Minimum requirements related to technical performance for IMT-2020 radio interfaces
- O-RAN Alliance specifications โ Open fronthaul and RAN architecture documents, as applicable to the target product
- IPC-6012 โ Qualification and Performance Specification for Rigid Printed Boards
- IPC-6018 โ Qualification and Performance Specification for High Frequency Printed Boards
- IPC-A-600 โ Acceptability of Printed Boards
- IPC-A-610 โ Acceptability of Electronic Assemblies
- IPC-TM-650 โ Test Methods Manual
- IPC-2221 โ Generic Standard on Printed Board Design
FAQ
What is the difference between a 5G NSA PCB and a 5G SA PCB?
A 5G NSA PCB is used in equipment where 5G NR works with LTE/EPC-based deployment assumptions, often through EN-DC. A 5G SA board belongs to equipment designed around a standalone 5G core architecture. At board level, the difference is not a single layout rule; it changes the network function, interface mix, validation scope and sometimes the coexistence burden.
Is every 5G NSA PCB a high-frequency PCB?
No. RF front-end boards and antenna-feed boards are high-frequency PCB problems, but DU, BBU-like and Cloud RAN boards may be dominated by high-speed digital channels, power integrity and thermal management. Many 5G NSA systems need both high-frequency and high-speed PCB expertise.
Can FR-4 be used in a 5G NSA PCB?
FR-4 may be acceptable for low-speed control, power or noncritical sections, but it is usually not the right choice for demanding RF paths or long high-speed channels where loss and Dk stability matter. Many designs use hybrid stackups so low-loss material is used only where it creates value.
When should Rogers or another low-loss RF material be used?
Use low-loss RF material when insertion loss, phase consistency, impedance stability, frequency range or antenna-feed performance cannot be met safely with standard material. The decision should be based on the RF path and test target, not simply on the presence of the term "5G."
Why is back-drilling important on 5G DU or BBU boards?
Back-drilling removes unused via stubs that can create reflections in high-speed channels. It is most valuable when the board is thick, the data rate is high, or the channel budget is tight. It should be specified when simulations or prior design rules show that the via stub is a real SI risk.
What is the biggest thermal risk in 5G small cell PCBs?
The biggest thermal risk is assuming that local thermal vias or thicker copper alone will solve heat. The heat must travel from the package into copper, through the PCB or heat spreader, across a thermal interface, and into the chassis or heat sink. If any part of that chain is weak, the board can still run too hot.
What should I send for a 5G NSA PCB quote?
Send Gerber or ODB++/IPC-2581 files, drill data, stackup intent, controlled-impedance table, RF frequency range, high-speed interface list, thermal load assumptions, material preferences, test requirements, assembly files and target quantity. For RF boards, include S-parameter or VNA expectations if they are required.
Can HILPCB support both bare PCB and assembled 5G telecom boards?
Yes. HILPCB can support bare PCB fabrication and turnkey assembly workflows for many telecom PCB builds, including RF shields, fine-pitch ICs, thermal interfaces, inspection planning and functional-test coordination where the customer provides the required test specification.
Next steps
If your 5G NSA project already has RF bands, high-speed interfaces, thermal sources and enclosure constraints defined, the next step is not another generic material discussion. It is a stackup, DFM, SI/PI, RF and thermal review tied to your actual board function.
Send your Gerber or ODB++ package, stackup intent, RF/high-speed requirements, thermal assumptions and production target to [email protected], or upload the files through the Quote page. HILPCB can review whether the project belongs in a Rogers or other high-frequency route, a high-speed multilayer route, an HDI route, a heavy-copper thermal route, or a controlled hybrid stackup before prototype cost is locked in.